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Commit f4b23cc2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  drm/r600: fix possible NULL pointer derefernce
  drm/radeon/kms: add quirk for ASUS HD 3600 board
  include/linux/vgaarb.h: add missing part of include guard
  drm/nouveau: Fix crashes during fbcon init on single head cards.
  drm/nouveau: fix pcirom vbios shadow breakage from acpi rom patch
  drm/radeon/kms: fix shared ddc harder
  drm/i915: enable low power render writes on GEN3 hardware.
  drm/i915: Define MI_ARB_STATE bits
  vmwgfx: return -EFAULT if copy_to_user fails
  fb: handle allocation failure in alloc_apertures()
  drm: radeon: check kzalloc() result
  drm/ttm: Fix build on architectures without AGP
  drm/radeon/kms: fix gtt MC base alignment on rs4xx/rs690/rs740 asics
  drm/radeon/kms: fix possible mis-detection of sideport on rs690/rs740
  drm/radeon/kms: fix legacy tv-out pal mode
parents e0959371 c42750b0

drivers/gpu/drm/i915/i915_gem.c

+10 −0
Original line number Diff line number Diff line
@@ -4742,6 +4742,16 @@ i915_gem_load(struct drm_device *dev) 
	list_add(&dev_priv->mm.shrink_list, &shrink_list);

	spin_unlock(&shrink_list_lock);



	/* On GEN3 we really need to make sure the ARB C3 LP bit is set */

	if (IS_GEN3(dev)) {

		u32 tmp = I915_READ(MI_ARB_STATE);

		if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {

			/* arb state is a masked write, so set bit + bit in mask */

			tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);

			I915_WRITE(MI_ARB_STATE, tmp);

		}

	}



	/* Old X drivers will take 0-2 for front, back, depth buffers */

	if (!drm_core_check_feature(dev, DRIVER_MODESET))

		dev_priv->fence_reg_start = 3;

drivers/gpu/drm/i915/i915_reg.h

+64 −0
Original line number Diff line number Diff line
@@ -359,6 +359,70 @@ 
#define LM_BURST_LENGTH     0x00000700

#define LM_FIFO_WATERMARK   0x0000001F

#define MI_ARB_STATE	0x020e4 /* 915+ only */

#define   MI_ARB_MASK_SHIFT	  16	/* shift for enable bits */



/* Make render/texture TLB fetches lower priorty than associated data

 *   fetches. This is not turned on by default

 */

#define   MI_ARB_RENDER_TLB_LOW_PRIORITY	(1 << 15)



/* Isoch request wait on GTT enable (Display A/B/C streams).

 * Make isoch requests stall on the TLB update. May cause

 * display underruns (test mode only)

 */

#define   MI_ARB_ISOCH_WAIT_GTT			(1 << 14)



/* Block grant count for isoch requests when block count is

 * set to a finite value.

 */

#define   MI_ARB_BLOCK_GRANT_MASK		(3 << 12)

#define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */

#define   MI_ARB_BLOCK_GRANT_4			(1 << 12)	/* for 2 display planes */

#define   MI_ARB_BLOCK_GRANT_2			(2 << 12)	/* for 1 display plane */

#define   MI_ARB_BLOCK_GRANT_0			(3 << 12)	/* don't use */



/* Enable render writes to complete in C2/C3/C4 power states.

 * If this isn't enabled, render writes are prevented in low

 * power states. That seems bad to me.

 */

#define   MI_ARB_C3_LP_WRITE_ENABLE		(1 << 11)



/* This acknowledges an async flip immediately instead

 * of waiting for 2TLB fetches.

 */

#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE	(1 << 10)



/* Enables non-sequential data reads through arbiter

 */

#define   MI_ARB_DUAL_DATA_PHASE_DISABLE       	(1 << 9)



/* Disable FSB snooping of cacheable write cycles from binner/render

 * command stream

 */

#define   MI_ARB_CACHE_SNOOP_DISABLE		(1 << 8)



/* Arbiter time slice for non-isoch streams */

#define   MI_ARB_TIME_SLICE_MASK		(7 << 5)

#define   MI_ARB_TIME_SLICE_1			(0 << 5)

#define   MI_ARB_TIME_SLICE_2			(1 << 5)

#define   MI_ARB_TIME_SLICE_4			(2 << 5)

#define   MI_ARB_TIME_SLICE_6			(3 << 5)

#define   MI_ARB_TIME_SLICE_8			(4 << 5)

#define   MI_ARB_TIME_SLICE_10			(5 << 5)

#define   MI_ARB_TIME_SLICE_14			(6 << 5)

#define   MI_ARB_TIME_SLICE_16			(7 << 5)



/* Low priority grace period page size */

#define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */

#define   MI_ARB_LOW_PRIORITY_GRACE_8KB		(1 << 4)



/* Disable display A/B trickle feed */

#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE	(1 << 2)



/* Set display plane priority */

#define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */

#define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */



#define CACHE_MODE_0	0x02120 /* 915+ only */

#define   CM0_MASK_SHIFT          16

#define   CM0_IZ_OPT_DISABLE      (1<<6)

drivers/gpu/drm/nouveau/nouveau_bios.c

+9 −24
Original line number Diff line number Diff line
@@ -203,36 +203,26 @@ struct methods { 
	const bool rw;

};



static struct methods nv04_methods[] = {

	{ "PROM", load_vbios_prom, false },

	{ "PRAMIN", load_vbios_pramin, true },

	{ "PCIROM", load_vbios_pci, true },

};



static struct methods nv50_methods[] = {

	{ "ACPI", load_vbios_acpi, true },

static struct methods shadow_methods[] = {

	{ "PRAMIN", load_vbios_pramin, true },

	{ "PROM", load_vbios_prom, false },

	{ "PCIROM", load_vbios_pci, true },

	{ "ACPI", load_vbios_acpi, true },

};



#define METHODCNT 3



static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)

{

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct methods *methods;

	int i;

	const int nr_methods = ARRAY_SIZE(shadow_methods);

	struct methods *methods = shadow_methods;

	int testscore = 3;

	int scores[METHODCNT];

	int scores[nr_methods], i;



	if (nouveau_vbios) {

		methods = nv04_methods;

		for (i = 0; i < METHODCNT; i++)

		for (i = 0; i < nr_methods; i++)

			if (!strcasecmp(nouveau_vbios, methods[i].desc))

				break;



		if (i < METHODCNT) {

		if (i < nr_methods) {

			NV_INFO(dev, "Attempting to use BIOS image from %s\n",

				methods[i].desc);
@@ -244,12 +234,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 
		NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);

	}



	if (dev_priv->card_type < NV_50)

		methods = nv04_methods;

	else

		methods = nv50_methods;



	for (i = 0; i < METHODCNT; i++) {

	for (i = 0; i < nr_methods; i++) {

		NV_TRACE(dev, "Attempting to load BIOS image from %s\n",

			 methods[i].desc);

		data[0] = data[1] = 0;	/* avoid reuse of previous image */
@@ -260,7 +245,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) 
	}



	while (--testscore > 0) {

		for (i = 0; i < METHODCNT; i++) {

		for (i = 0; i < nr_methods; i++) {

			if (scores[i] == testscore) {

				NV_TRACE(dev, "Using BIOS image from %s\n",

					 methods[i].desc);

drivers/gpu/drm/nouveau/nouveau_fbcon.c

+2 −1
Original line number Diff line number Diff line
@@ -387,7 +387,8 @@ int nouveau_fbcon_init(struct drm_device *dev) 
	dev_priv->nfbdev = nfbdev;

	nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs;



	ret = drm_fb_helper_init(dev, &nfbdev->helper, 2, 4);

	ret = drm_fb_helper_init(dev, &nfbdev->helper,

				 nv_two_heads(dev) ? 2 : 1, 4);

	if (ret) {

		kfree(nfbdev);

		return ret;

drivers/gpu/drm/radeon/r100.c

+1 −0
Original line number Diff line number Diff line
@@ -2354,6 +2354,7 @@ void r100_mc_init(struct radeon_device *rdev) 
	if (rdev->flags & RADEON_IS_IGP)

		base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;

	radeon_vram_location(rdev, &rdev->mc, base);

	rdev->mc.gtt_base_align = 0;

	if (!(rdev->flags & RADEON_IS_AGP))

		radeon_gtt_location(rdev, &rdev->mc);

	radeon_update_bandwidth_info(rdev);