Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f485565e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Add jtag_mm nodes for monaco"

parents 3f7a9d1a aa76d43b

qcom/monaco.dtsi

+44 −0
Original line number Diff line number Diff line
@@ -1127,6 +1127,50 @@ 
		};

	};



	jtag_mm0: jtagmm@9040000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9040000 0x1000>;

		reg-names = "etm-base";



		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};



	jtag_mm1: jtagmm@9140000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9140000 0x1000>;

		reg-names = "etm-base";



		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU1>;

	};



	jtag_mm2: jtagmm@9240000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9240000 0x1000>;

		reg-names = "etm-base";



		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU2>;

	};



	jtag_mm3: jtagmm@9340000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9340000 0x1000>;

		reg-names = "etm-base";



		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";



		qcom,coresight-jtagmm-cpu = <&CPU3>;

	};



	clk_virt: interconnect {

		compatible = "qcom,monaco-clk_virt";

		#interconnect-cells = <1>;