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Commit f3ff6149 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Enable L3 interconnect driver for scshrike"

parents 97be6d1c b1ed71a1

qcom/sdmshrike.dtsi

+26 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <dt-bindings/clock/qcom,videocc-sm8150.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/interconnect/qcom,icc.h>

#include <dt-bindings/interconnect/qcom,osm-l3.h>

#include <dt-bindings/interconnect/qcom,scshrike.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -39,6 +40,7 @@ 
			capacity-dmips-mhz = <1024>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			#cooling-cells = <2>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";
@@ -72,6 +74,7 @@ 
			capacity-dmips-mhz = <1024>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_1>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			#cooling-cells = <2>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";
@@ -99,6 +102,7 @@ 
			capacity-dmips-mhz = <1024>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_2>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			#cooling-cells = <2>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";
@@ -126,6 +130,7 @@ 
			capacity-dmips-mhz = <1024>;

			cache-size = <0x8000>;

			next-level-cache = <&L2_3>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			#cooling-cells = <2>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";
@@ -153,6 +158,7 @@ 
			capacity-dmips-mhz = <1740>;

			cache-size = <0x20000>;

			next-level-cache = <&L2_4>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			#cooling-cells = <2>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";
@@ -180,6 +186,7 @@ 
			capacity-dmips-mhz = <1740>;

			cache-size = <0x20000>;

			next-level-cache = <&L2_5>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			#cooling-cells = <2>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";
@@ -207,6 +214,7 @@ 
			capacity-dmips-mhz = <1740>;

			cache-size = <0x20000>;

			next-level-cache = <&L2_6>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			#cooling-cells = <2>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";
@@ -234,6 +242,7 @@ 
			capacity-dmips-mhz = <1740>;

			cache-size = <0x20000>;

			next-level-cache = <&L2_7>;

			qcom,freq-domain = <&cpufreq_hw 1 4>;

			#cooling-cells = <2>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";
@@ -708,6 +717,14 @@ 
		};

	};



	osm_l3: interconnect@18321000 {

		reg = <0x18321000 0x1400>;

		compatible = "qcom,scshrike-osm-l3";

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		#interconnect-cells = <1>;

	};



	config_noc: interconnect@1500000 {

		reg = <0x1500000 0x7400>;

		compatible = "qcom,scshrike-config_noc";
@@ -948,6 +965,15 @@ 
		#clock-cells = <1>;

	};



	cpufreq_hw: cpufreq@18323000 {

		compatible = "qcom,cpufreq-hw";

		reg = <0x18323000 0x1400>, <0x18325800 0x1400>;

		reg-names = "freq-domain0", "freq-domain1";

		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		#freq-domain-cells = <2>;

	};



	tcsr_mutex_block: syscon@1f40000 {

		compatible = "syscon";

		reg = <0x1f40000 0x20000>;