Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f3d80deb authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
Browse files

ARM: dts: imx: add cooling-cells for cpufreq cooling device



Add #cooling-cells for i.MX6/7 SoCs for cpufreq cooling device usage.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarBastian Stender <bst@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 328bd825
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@
				396000	1175000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			#cooling-cells = <2>;
			clocks = <&clks IMX6QDL_CLK_ARM>,
				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
				 <&clks IMX6QDL_CLK_STEP>,
+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@
				396000	1175000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			#cooling-cells = <2>;
			clocks = <&clks IMX6QDL_CLK_ARM>,
				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
				 <&clks IMX6QDL_CLK_STEP>,
+1 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@
				396000          1175000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			#cooling-cells = <2>;
			clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
					<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
					<&clks IMX6SL_CLK_PLL1_SYS>;
+1 −0
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@
				198000	    1175000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			#cooling-cells = <2>;
			clocks = <&clks IMX6SX_CLK_ARM>,
				 <&clks IMX6SX_CLK_PLL2_PFD2>,
				 <&clks IMX6SX_CLK_STEP>,
+1 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@
			device_type = "cpu";
			reg = <0>;
			clock-latency = <61036>; /* two CLK32 periods */
			#cooling-cells = <2>;
			operating-points = <
				/* kHz	uV */
				696000	1275000
Loading