Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f36a0698 authored by Zheng Yang's avatar Zheng Yang Committed by Greg Kroah-Hartman
Browse files

phy/rockchip: inno-hdmi: round fractal pixclock in rk3328 recalc_rate 



[ Upstream commit d5ef343c1d62bc4c4c2c393af654a41cb34b449f ]

inno_hdmi_phy_rk3328_clk_recalc_rate() is returning a rate not found
in the pre pll config table when the fractal divider is used.
This can prevent proper power_on because a tmdsclock for the new rate
is not found in the pre pll config table.

Fix this by saving and returning a rounded pixel rate that exist
in the pre pll config table.

Fixes: 53706a11 ("phy: add Rockchip Innosilicon hdmi phy")
Signed-off-by: default avatarZheng Yang <zhengyang@rock-chips.com>
Signed-off-by: default avatarJonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20230615171005.2251032-3-jonas@kwiboo.se


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent b0d5d77b

drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

+5 −3
Original line number Diff line number Diff line
@@ -745,10 +745,12 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw, 
		do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));

	}



	inno->pixclock = vco;

	dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);

	inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;



	return vco;

	dev_dbg(inno->dev, "%s rate %lu vco %llu\n",

		__func__, inno->pixclock, vco);



	return inno->pixclock;

}



static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw,