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Commit f3500051 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1""

parents 65f4d0d9 58fe9100

msm/sde/sde_crtc.c

+0 −6
Original line number Diff line number Diff line
@@ -3325,11 +3325,6 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc, 


	if (crtc->state->mode_changed || sde_kms->perf.catalog->uidle_cfg.dirty)

		sde_core_perf_crtc_update_uidle(crtc, true);

	else if (!test_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask) &&

			!sde_kms->perf.uidle_enabled)

		sde_core_uidle_setup_ctl(crtc, false);



	test_and_clear_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask);



	/*

	 * Since CP properties use AXI buffer to program the
@@ -4003,7 +3998,6 @@ void sde_crtc_reset_sw_state(struct drm_crtc *crtc) 


	/* mark other properties which need to be dirty for next update */

	set_bit(SDE_CRTC_DIRTY_DIM_LAYERS, &sde_crtc->revalidate_mask);

	set_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask);

	if (cstate->num_ds_enabled)

		set_bit(SDE_CRTC_DIRTY_DEST_SCALER, cstate->dirty);

}

msm/sde/sde_crtc.h

+1 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2015-2021 The Linux Foundation. All rights reserved.

 * Copyright (C) 2013 Red Hat

 * Author: Rob Clark <robdclark@gmail.com>
@@ -399,7 +400,6 @@ struct sde_crtc { 
enum sde_crtc_dirty_flags {

	SDE_CRTC_DIRTY_DEST_SCALER,

	SDE_CRTC_DIRTY_DIM_LAYERS,

	SDE_CRTC_DIRTY_UIDLE,

	SDE_CRTC_DIRTY_MAX,

};

msm/sde/sde_hw_uidle.c

+5 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 *

 */
@@ -161,7 +162,7 @@ void sde_hw_uidle_setup_ctl(struct sde_hw_uidle *uidle, 
		struct sde_uidle_ctl_cfg *cfg)

{

	struct sde_hw_blk_reg_map *c = &uidle->hw;

	u32 reg_val;

	u32 reg_val, fal10_veto_regval = 0;



	reg_val = SDE_REG_READ(c, UIDLE_CTL);

	reg_val = (reg_val & ~BIT(31)) | (cfg->uidle_enable ? BIT(31) : 0);
@@ -176,6 +177,9 @@ void sde_hw_uidle_setup_ctl(struct sde_hw_uidle *uidle, 
		FAL10_EXIT_CNT_MSK);



	SDE_REG_WRITE(c, UIDLE_CTL, reg_val);

	if (!cfg->uidle_enable)

		fal10_veto_regval |= (BIT(31) | BIT(0));

	SDE_REG_WRITE(c, UIDLE_FAL10_VETO_OVERRIDE, fal10_veto_regval);

}



static void sde_hw_uilde_active_override(struct sde_hw_uidle *uidle,