Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f32ab754 authored by =?UTF-8?q?Christian=20K=C3=B6nig?='s avatar =?UTF-8?q?Christian=20K=C3=B6nig?= Committed by Bjorn Helgaas
Browse files

x86/PCI: Add "pci=big_root_window" option for AMD 64-bit windows 



Only try to enable a 64-bit window on AMD CPUs when "pci=big_root_window"
is specified.

This taints the kernel because the new 64-bit window uses address space we
don't know anything about, and it may contain unreported devices or memory
that would conflict with the window.

The pci_amd_enable_64bit_bar() quirk that enables the window is specific to
AMD CPUs.  The generic solution would be to have the firmware enable the
window and describe it in the host bridge's _CRS method, or at least
describe it in the _PRS method so the OS would have the option of enabling
it.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
[bhelgaas: changelog, extend doc, mention taint in dmesg]
Signed-off-by: default avatarBjorn Helgaas <helgaas@kernel.org>
parent 1291a0d5

Documentation/admin-guide/kernel-parameters.txt

+6 −0
Original line number Diff line number Diff line
@@ -3094,6 +3094,12 @@ 
		pcie_scan_all	Scan all possible PCIe devices.  Otherwise we

				only look for one device below a PCIe downstream

				port.

		big_root_window	Try to add a big 64bit memory window to the PCIe

				root complex on AMD CPUs. Some GFX hardware

				can resize a BAR to allow access to all VRAM.

				Adding the window is slightly risky (it may

				conflict with unreported devices), so this

				taints the kernel.



	pcie_aspm=	[PCIE] Forcibly enable or disable PCIe Active State Power

			Management.

arch/x86/include/asm/pci_x86.h

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ do { \ 
#define PCI_NOASSIGN_ROMS	0x80000

#define PCI_ROOT_NO_CRS		0x100000

#define PCI_NOASSIGN_BARS	0x200000

#define PCI_BIG_ROOT_WINDOW	0x400000



extern unsigned int pci_probe;

extern unsigned long pirq_table_addr;

arch/x86/pci/common.c

+5 −0
Original line number Diff line number Diff line
@@ -594,6 +594,11 @@ char *__init pcibios_setup(char *str) 
	} else if (!strcmp(str, "nocrs")) {

		pci_probe |= PCI_ROOT_NO_CRS;

		return NULL;

#ifdef CONFIG_PHYS_ADDR_T_64BIT

	} else if (!strcmp(str, "big_root_window")) {

		pci_probe |= PCI_BIG_ROOT_WINDOW;

		return NULL;

#endif

	} else if (!strcmp(str, "earlydump")) {

		pci_early_dump_regs = 1;

		return NULL;

arch/x86/pci/fixup.c

+6 −1
Original line number Diff line number Diff line
@@ -667,6 +667,9 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) 
	struct resource *res, *conflict;

	struct pci_dev *other;



	if (!(pci_probe & PCI_BIG_ROOT_WINDOW))

		return;



	/* Check that we are the only device of that type */

	other = pci_get_device(dev->vendor, dev->device, NULL);

	if (other != dev ||
@@ -714,7 +717,9 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev) 
		res->start = conflict->end + 1;

	}



	dev_info(&dev->dev, "adding root bus resource %pR\n", res);

	dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",

		 res);

	add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);



	base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |

		AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;