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Commit f312958f authored by Neel Patel's avatar Neel Patel Committed by Greg Kroah-Hartman
Browse files

ionic: clean interrupt before enabling queue to avoid credit race 



[ Upstream commit e8797a058466b60fc5a3291b92430c93ba90eaff ]

Clear the interrupt credits before enabling the queue rather
than after to be sure that the enabled queue starts at 0 and
that we don't wipe away possible credits after enabling the
queue.

Fixes: 0f3154e6 ("ionic: Add Tx and Rx handling")
Signed-off-by: default avatarNeel Patel <neel.patel@amd.com>
Signed-off-by: default avatarShannon Nelson <shannon.nelson@amd.com>
Reviewed-by: default avatarLeon Romanovsky <leonro@nvidia.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent a532f7eb

drivers/net/ethernet/pensando/ionic/ionic_lif.c

+12 −3
Original line number Diff line number Diff line
@@ -190,6 +190,7 @@ static int ionic_qcq_enable(struct ionic_qcq *qcq) 
			.oper = IONIC_Q_ENABLE,

		},

	};

	int ret;



	idev = &lif->ionic->idev;

	dev = lif->ionic->dev;
@@ -197,16 +198,24 @@ static int ionic_qcq_enable(struct ionic_qcq *qcq) 
	dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n",

		ctx.cmd.q_control.index, ctx.cmd.q_control.type);



	if (qcq->flags & IONIC_QCQ_F_INTR)

		ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);



	ret = ionic_adminq_post_wait(lif, &ctx);

	if (ret)

		return ret;



	if (qcq->napi.poll)

		napi_enable(&qcq->napi);



	if (qcq->flags & IONIC_QCQ_F_INTR) {

		irq_set_affinity_hint(qcq->intr.vector,

				      &qcq->intr.affinity_mask);

		napi_enable(&qcq->napi);

		ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);

		ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,

				IONIC_INTR_MASK_CLEAR);

	}



	return ionic_adminq_post_wait(lif, &ctx);

	return 0;

}



static int ionic_qcq_disable(struct ionic_qcq *qcq)