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Commit f2e7bfbb authored by Diana Craciun's avatar Diana Craciun Committed by Scott Wood
Browse files

powerpc/fsl: Updated device trees for platforms with corenet version 2 



Updated the device trees according to the corenet-cf
binding definition.

Signed-off-by: default avatarDiana Craciun <Diana.Craciun@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent 385510be

arch/powerpc/boot/dts/b4860emu.dts

+6 −1
Original line number Original line Diff line number Diff line
@@ -61,21 +61,25 @@ 
			device_type = "cpu";

			device_type = "cpu";

			reg = <0 1>;

			reg = <0 1>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2>;

			fsl,portid-mapping = <0x80000000>;

		};

		};

		cpu1: PowerPC,e6500@2 {

		cpu1: PowerPC,e6500@2 {

			device_type = "cpu";

			device_type = "cpu";

			reg = <2 3>;

			reg = <2 3>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2>;

			fsl,portid-mapping = <0x80000000>;

		};

		};

		cpu2: PowerPC,e6500@4 {

		cpu2: PowerPC,e6500@4 {

			device_type = "cpu";

			device_type = "cpu";

			reg = <4 5>;

			reg = <4 5>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2>;

			fsl,portid-mapping = <0x80000000>;

		};

		};

		cpu3: PowerPC,e6500@6 {

		cpu3: PowerPC,e6500@6 {

			device_type = "cpu";

			device_type = "cpu";

			reg = <6 7>;

			reg = <6 7>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2>;

			fsl,portid-mapping = <0x80000000>;

		};

		};

	};

	};

};

};
@@ -157,7 +161,7 @@ 
	};

	};





	corenet-cf@18000 {

	corenet-cf@18000 {

		compatible = "fsl,b4-corenet-cf";

		compatible = "fsl,corenet2-cf", "fsl,corenet-cf";

		reg = <0x18000 0x1000>;

		reg = <0x18000 0x1000>;

		interrupts = <16 2 1 0>;

		interrupts = <16 2 1 0>;

		fsl,ccf-num-csdids = <32>;

		fsl,ccf-num-csdids = <32>;
@@ -167,6 +171,7 @@ 
	iommu@20000 {

	iommu@20000 {

		compatible = "fsl,pamu-v1.0", "fsl,pamu";

		compatible = "fsl,pamu-v1.0", "fsl,pamu";

		reg = <0x20000 0x4000>;

		reg = <0x20000 0x4000>;

		fsl,portid-mapping = <0x8000>;

		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <1>;

		#size-cells = <1>;

		interrupts = <

		interrupts = <

arch/powerpc/boot/dts/fsl/b4420si-post.dtsi

+0 −4
Original line number Original line Diff line number Diff line
@@ -76,10 +76,6 @@ 
		compatible = "fsl,b4420-l3-cache-controller", "cache";

		compatible = "fsl,b4420-l3-cache-controller", "cache";

	};

	};





	corenet-cf@18000 {

		compatible = "fsl,b4420-corenet-cf";

	};



	guts: global-utilities@e0000 {

	guts: global-utilities@e0000 {

		compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";

		compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";

	};

	};

arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi

+2 −0
Original line number Original line Diff line number Diff line
@@ -66,12 +66,14 @@ 
			reg = <0 1>;

			reg = <0 1>;

			clocks = <&mux0>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2>;

			fsl,portid-mapping = <0x80000000>;

		};

		};

		cpu1: PowerPC,e6500@2 {

		cpu1: PowerPC,e6500@2 {

			device_type = "cpu";

			device_type = "cpu";

			reg = <2 3>;

			reg = <2 3>;

			clocks = <&mux0>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2>;

			fsl,portid-mapping = <0x80000000>;

		};

		};

	};

	};

};
 
};

arch/powerpc/boot/dts/fsl/b4860si-post.dtsi

+0 −4
Original line number Original line Diff line number Diff line
@@ -120,10 +120,6 @@ 
		compatible = "fsl,b4860-l3-cache-controller", "cache";

		compatible = "fsl,b4860-l3-cache-controller", "cache";

	};

	};





	corenet-cf@18000 {

		compatible = "fsl,b4860-corenet-cf";

	};



	guts: global-utilities@e0000 {

	guts: global-utilities@e0000 {

		compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";

		compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";

	};

	};

arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi

+4 −0
Original line number Original line Diff line number Diff line
@@ -66,24 +66,28 @@ 
			reg = <0 1>;

			reg = <0 1>;

			clocks = <&mux0>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2>;

			fsl,portid-mapping = <0x80000000>;

		};

		};

		cpu1: PowerPC,e6500@2 {

		cpu1: PowerPC,e6500@2 {

			device_type = "cpu";

			device_type = "cpu";

			reg = <2 3>;

			reg = <2 3>;

			clocks = <&mux0>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2>;

			fsl,portid-mapping = <0x80000000>;

		};

		};

		cpu2: PowerPC,e6500@4 {

		cpu2: PowerPC,e6500@4 {

			device_type = "cpu";

			device_type = "cpu";

			reg = <4 5>;

			reg = <4 5>;

			clocks = <&mux0>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2>;

			fsl,portid-mapping = <0x80000000>;

		};

		};

		cpu3: PowerPC,e6500@6 {

		cpu3: PowerPC,e6500@6 {

			device_type = "cpu";

			device_type = "cpu";

			reg = <6 7>;

			reg = <6 7>;

			clocks = <&mux0>;

			clocks = <&mux0>;

			next-level-cache = <&L2>;

			next-level-cache = <&L2>;

			fsl,portid-mapping = <0x80000000>;

		};

		};

	};

	};

};
 
};