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Commit f256922e authored by Raghavendra Rao Ananta's avatar Raghavendra Rao Ananta
Browse files

ARM: dts: msm: Reorganize the pinctrl node 

As the size of the lahaina-pinctrl.dtsi file is huge, it's
possible that the config nodes might be placed incorrectly
under &soc{..}, instead of &tlmm{..} due to human errors.
Hence, rearrange the node such that the lahaina-pinctrl.dtsi
file itself begin with the &tlmm block to minimize these errors.

Change-Id: I537e6cc980d58470949fc99dcaa4e65b0ff75663
parent 5402f200

qcom/lahaina-pinctrl.dtsi

+1462 −1473
Original line number Diff line number Diff line 
&soc {

	tlmm: pinctrl@f000000 {

		compatible = "qcom,lahaina-pinctrl";

		reg = <0x0F000000 0x1000000>;

		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

		wakeup-parent = <&pdc>;



&tlmm {

	bt_en_sleep: bt_en_sleep {

		mux {

			pins = "gpio65";
@@ -1657,7 +1647,7 @@ 
			};

		};

	};

	};



	pmx_sde: pmx_sde {

		sde_dsi_active: sde_dsi_active {

			mux {
@@ -2198,5 +2188,4 @@ 
			};

		};

	};



};

qcom/lahaina.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -668,6 +668,17 @@ 
		reg-names = "pshold-base", "tcsr-boot-misc-detect";

	};



	tlmm: pinctrl@f000000 {

		compatible = "qcom,lahaina-pinctrl";

		reg = <0x0F000000 0x1000000>;

		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

		wakeup-parent = <&pdc>;

	};



	ipcc_mproc: qcom,ipcc@408000 {

		compatible = "qcom,ipcc";

		reg = <0x408000 0x1000>;