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Commit f20d0ab2 authored by Linux Build Service Account's avatar Linux Build Service Account
Browse files

Merge 1b7f8726 on remote branch 

Change-Id: I4f0b096caa614c7590c233e78745fffa6029f5b5
parents 83c17948 29b029ee

bindings/sde-dp.txt

+0 −4
Original line number Diff line number Diff line
@@ -72,8 +72,6 @@ DP Controller: Required properties: 
- qcom,mst-enable:		MST feature enable control node.

- qcom,dsc-feature-enable:	DSC feature enable control node.

- qcom,fec-feature-enable:	FEC feature enable control node.

- qcom,max-dp-dsc-blks:		An integer specifying the max. DSC blocks available for Display port.

- qcom,max-dp-dsc-input-width-pixs: An integer specifying the max. input width of pixels for each DSC block.

- qcom,altmode-dev:         Phandle for the AltMode GLink driver.

- usb-controller:         Phandle for the USB controller.

- qcom,pll-revision:    PLL hardware revision.
@@ -199,8 +197,6 @@ sde_dp: qcom,dp_display@0 { 
	qcom,mst-enable;

	qcom,dsc-feature-enable;

	qcom,fec-feature-enable;

	qcom,max-dp-dsc-blks = <2>;

	qcom,max-dp-dsc-input-width-pixs = <2048>;



	vdda-1p2-supply = <&L6B>;

	vdda-0p9-supply = <&L1B>;

bindings/sde.txt

+41 −10
Original line number Diff line number Diff line
@@ -124,15 +124,20 @@ Optional properties: 
- qcom,sde-sspp-scale-size:	A u32 value indicates the scaling block size on sspp.

- qcom,sde-mixer-blendstages:	A u32 value indicates the max mixer blend stages for

				alpha blending.

- qcom,sde-qseed-type:		A string entry indiates qseed support on sspp and wb.

				It supports "qssedv3" and "qseedv2" entries for qseed

				type. By default "qseedv2" is used if this optional property

				is not defined.

- qcom,sde-qseed-sw-lib-rev:	A string entry indicates qseed sw library revision

				supporting the qseed HW block. It supports

				"qseedv3", "qseedv3lite" and "qseedv2" entries for qseed

				revision. By default "qseedv2" is used if this

				optional property is not defined.

- qcom,sde-qseed-scalar-version: A u32 value indicating the HW version of the

				 QSEED hardware block

- qcom,sde-csc-type:		A string entry indicates csc support on sspp and wb.

				It supports "csc" and "csc-10bit" entries for csc

				type.

- qcom,sde-highest-bank-bit:	A u32 property to indicate GPU/Camera/Video highest memory

				bank bit used for tile format buffers.

- qcom,sde-highest-bank-bit:	Property to specify GPU/Camera/Video highest memory

				bank bit used for tile format buffers. First value

				in the array represents the ddr type and the second

				value is the hbb value corresponding to the ddr type.

- qcom,sde-ubwc-version:	Property to specify the UBWC feature version.

- qcom,sde-ubwc-static:	Property to specify the default UBWC static

				configuration value.
@@ -175,10 +180,10 @@ Optional properties: 
				match the number of offsets defined in

				property: qcom,sde-sspp-off

- qcom,sde-sspp-clk-status:	Array of offsets describing clk status

				offsets for dynamic clock gating. 1st value

				offsets for clock active state. 1st value

				in the array represents offset of the status

				register. 2nd value represents bit offset within

				control register. Number of offsets defined should

				status register. Number of offsets defined should

				match the number of offsets defined in

				property: qcom,sde-sspp-off.

- qcom,sde-sspp-excl-rect:	Array of u32 values indicating exclusion rectangle
@@ -236,6 +241,7 @@ Optional properties: 
- qcom,sde-dsc-native422-supp:	Array of flags indicating whether corresponding dsc

				block can support native 422 and native 420

				encoding.

- qcom,sde-dsc-linewidth:	A u32 value indicates the max dsc line width.

- qcom,sde-vdc-off:		A u32 offset address for the available vdc blocks.

						This offset is calculated from register "mdp_phys"

						defined in reg property.
@@ -355,6 +361,13 @@ Optional properties: 
				control register. Number of offsets defined should

				match the number of offsets defined in

				property: qcom,sde-wb-off

- qcom,sde-wb-clk-status:	Array of 2 cell property describing clk status

				offsets for clock active state. 1st value

				in the array represents offset of the status

				register. 2nd value represents bit offset within

				status register. Number of offsets defined should

				match the number of offsets defined in

				property: qcom,sde-wb-off

- qcom,sde-reg-dma-off:         Array of u32 offset addresses of the dma hardware blocks,

				relative to "regdma_phys" defined in reg property.

- qcom,sde-reg-dma-id:		Array of u32 DMA block type ids corresponding to the
@@ -472,6 +485,7 @@ Optional properties: 
					0xf represents 4 cpu cores. These cores can be

					silver or gold or gold+.

- qcom,sde-qos-cpu-dma-latency:	A u32 value indicating desired PM QoS CPU DMA latency in usec.

- qcom,sde-qos-cpu-irq-latency:	A u32 value indicating desired PM QoS CPU irq latency in usec.

- qcom,sde-inline-rot-xin:	An integer array of xin-ids related to inline

				rotation.

- qcom,sde-inline-rot-xin-type:	A string array indicating the type of xin,
@@ -505,6 +519,15 @@ Optional properties: 
				ordering block

				0: lower priority pipe has to be on the left for a given pair of pipes.

				1: priority have to be explicitly configured for a given pair of pipes.

- qcom,sde-trusted-vm-env:	Boolean property to indicate if the device

				driver is executing in a trusted VM

- qcom,sde-max-trusted-vm-displays:    A u32 property to indicate the maximum

				number of concurrent displays supported in the

	                        trusted vm environment

- qcom,sde-vm-exclude-reg-names A string array indicating the reg-names which

				should be excluded from IO memory validation list

				in trusted vm environment

- qcom,vram-size: 		A u32 value indicating the size of the VRAM in bytes



Bus Scaling:

- interconnects                 An array of 4 cell properties with the format of
@@ -661,7 +684,8 @@ Example: 
    qcom,sde-mixer-linewidth = <2560>;

    qcom,sde-sspp-linewidth = <2560>;

    qcom,sde-mixer-blendstages = <0x7>;

    qcom,sde-highest-bank-bit = <0x2>;

    qcom,sde-dsc-linewidth = <2048>;

    qcom,sde-highest-bank-bit = <0x7 0x2>;

    qcom,sde-ubwc-version = <0x100>;

    qcom,sde-ubwc-static = <0x100>;

    qcom,sde-ubwc-swizzle = <0>;
@@ -688,13 +712,15 @@ Example: 
    qcom,sde-wb-linewidth-linear = <5120>;

    qcom,sde-sspp-scale-size = <0x100>;

    qcom,sde-mixer-blendstages = <0x8>;

    qcom,sde-qseed-type = "qseedv2";

    qcom,sde-qseed-sw-lib-rev = "qseedv2";

    qcom,sde-qseed-scalar-version = <0x3000>;

    qcom,sde-csc-type = "csc-10bit";

    qcom,sde-highest-bank-bit = <15>;

    qcom,sde-has-mixer-gc;

    qcom,sde-has-idle-pc;

    qcom,fullsize-va-map;

    qcom,sde-has-dest-scaler;

    qcom,sde-max-trusted-vm-displays = <1>;

    qcom,sde-max-dest-scaler-input-linewidth = <2048>;

    qcom,sde-max-dest-scaler-output-linewidth = <2560>;

    qcom,sde-sspp-max-rects = <1 1 1 1
@@ -714,9 +740,11 @@ Example: 
    qcom,sde-te2-off = <0x100>;

    qcom,sde-te-size = <0xffff>;

    qcom,sde-te2-size = <0xffff>;

    qcom,sde-trusted-vm-env;



    qcom,sde-wb-id = <2>;

    qcom,sde-wb-clk-ctrl = <0x2bc 16>;

    qcom,sde-wb-clk-status = <0x3bc 20>;



    qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000

		0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff
@@ -738,6 +766,7 @@ Example: 
    qcom,sde-qos-cpu-mask = <0x3>;

    qcom,sde-qos-cpu-mask-performance = <0xf>;

    qcom,sde-qos-cpu-dma-latency = <300>;

    qcom,sde-qos-cpu-irq-latency = <300>;



    qcom,sde-vbif-off = <0 0>;

    qcom,sde-vbif-id = <0 1>;
@@ -778,6 +807,8 @@ Example: 
    qcom,sde-amortizable-threshold = <11>;

    qcom,sde-secure-sid-mask = <0x200801 0x200c01>;



    qcom,vram-size = <0x200000>;



    qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;

    qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;

    qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;

display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi

+87 −12
Original line number Diff line number Diff line
@@ -35,6 +35,11 @@ 
		qcom,mdss-dsi-te-dcs-command = <1>;

		qcom,mdss-dsi-te-check-enable;

		qcom,mdss-dsi-te-using-te-pin;

		qcom,mdss-dsi-panel-hdr-enabled;

		qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000

			17000 15500 30000 8000 3000>;

		qcom,mdss-dsi-panel-peak-brightness = <4200000>;

		qcom,mdss-dsi-panel-blackness-level = <3230>;

		qcom,mdss-dsi-display-timings {

			timing@0 {

				qcom,mdss-dsi-panel-framerate = <60>;
@@ -62,17 +67,46 @@ 


				qcom,mdss-dsi-on-command = [

					39 01 00 00 00 00 02 b0 00

					39 01 00 00 00 00 13 d8 00 00 00 00 00

					   00 00 00 00 5b 00 5b 00 5b 00 5b 00

					   5b

					39 01 00 00 00 00 0c c2 09 24 0c 00 00

					   0c 00 00 00 09 3c

					39 01 00 00 00 00 1a d7 00 b9 3c 00 40

					   04 00 a0 0a 00 40 00 00 00 00 00 00

					   19 3c 00 40 04 00 a0 0a

					39 01 00 00 00 00 02 b0 80

					39 01 00 00 00 00 02 e6 00

					39 01 00 00 00 00 14 de 40 00 18 00 18

					   00 18 00 18 10 00 18 00 18 00 18 02

					   00 00

					39 01 00 00 00 00 02 b0 04

					39 01 00 00 00 00 03 e8 00 02

					39 01 00 00 00 00 03 e4 00 08

					39 01 00 00 00 00 02 b0 00

					39 01 00 00 00 00 11 c4 00 00 00 00

					   00 00 00 00 00 00 00 02 00 00 00 32

					39 01 00 00 00 00 19 cf 64 0b 00 00 00

					   00 00 00 08 00 0b 77 01 01 01 01 01

					   01 04 04 04 04 04 05

					39 01 00 00 00 00 02 b0 04

					   01 02 02 02 02 02 03

					39 01 00 00 00 00 15 d3 45 00 00 01 13

					   15 00 15 07 0f 77 77 77 37 b2 11 00

					   a0 3c 9c

					39 01 00 00 00 00 1a d7 00 b9 34 00 40

					   04 00 a0 0a 00 40 00 00 00 00 00 00

					   19 34 00 40 04 00 a0 0a

					39 01 00 00 00 00 34 d8 00 00 00 00 00

					   00 00 00 00 3a 00 3a 00 3a 00 3a 00

					   3a 05 00 00 00 00 00 00 00 00 00 0a

					   00 0a 00 00 00 00 00 00 00 00 00 00

					   00 00 00 0a 00 32 00 0a 00 22

					39 01 00 00 00 00 2b df 50 42 58 81 2d

					   00 00 00 00 00 00 6b 00 00 00 00 00

					   00 00 00 01 0f ff d4 0e 00 00 00 00

					   00 00 0f 53 f1 00 00 00 00 00 00 00

					   00

					39 01 00 00 00 00 02 f7 01

					39 01 00 00 00 00 02 b0 80

					39 01 00 00 00 00 0a e4 34 b4 00 00 00

					   39 04 09 34

					39 01 00 00 00 00 02 e6 00

					39 01 00 00 00 00 02 b0 04

					39 01 00 00 00 00 03 df 50 40

					39 01 00 00 00 00 06 f3 50 00 00 00 00

					39 01 00 00 00 00 02 f2 11
@@ -84,7 +118,11 @@ 
					39 01 00 00 00 00 05 2a 00 00 04 37

					39 01 00 00 00 00 05 2b 00 00 09 23

					05 01 00 00 78 00 01 11

					05 01 00 00 00 00 01 29

					05 01 00 00 14 00 01 29

					39 01 00 00 00 00 02 b0 00

					39 01 00 00 00 00 1a c2 09 24 0c 00 00

					   0c 09 3c 00 09 3c 00 00 00 00 00 00

					   00 00 00 00 00 30 00 6c

				];



				qcom,mdss-dsi-off-command = [
@@ -129,14 +167,47 @@ 
				];



				qcom,mdss-dsi-on-command = [

					39 01 00 00 00 00 02 b0 00

					39 01 00 00 00 00 0c c2 09 24 0c 00 00

					   0c 00 00 00 09 3c

					39 01 00 00 00 00 1a d7 00 b9 3c 00 40

					   04 00 a0 0a 00 40 00 00 00 00 00 00

					   19 3c 00 40 04 00 a0 0a

					39 01 00 00 00 00 02 b0 80

					39 01 00 00 00 00 02 e6 00

					39 01 00 00 00 00 14 de 40 00 18 00 18

					   00 18 00 18 10 00 18 00 18 00 18 02

					   00 00

					39 01 00 00 00 00 02 b0 04

					39 01 00 00 00 00 03 e8 00 02

					39 01 00 00 00 00 03 e4 00 08

					39 01 00 00 00 00 02 b0 00

					39 01 00 00 00 00 11 c4 00 00 00 00

					   00 00 00 00 00 00 00 02 00 00 00 32

					39 01 00 00 00 00 19 cf 64 0b 00 00 00

					   00 00 00 08 00 0b 77 01 01 01 01 01

					   01 04 04 04 04 04 05

					39 01 00 00 00 00 02 b0 04

					   01 02 02 02 02 02 03

					39 01 00 00 00 00 15 d3 45 00 00 01 13

					   15 00 15 07 0f 77 77 77 37 b2 11 00

					   a0 3c 9c

					39 01 00 00 00 00 1a d7 00 b9 34 00 40

					   04 00 a0 0a 00 40 00 00 00 00 00 00

					   19 34 00 40 04 00 a0 0a

					39 01 00 00 00 00 34 d8 00 00 00 00 00

					   00 00 00 00 3a 00 3a 00 3a 00 3a 00

					   3a 05 00 00 00 00 00 00 00 00 00 0a

					   00 0a 00 00 00 00 00 00 00 00 00 00

					   00 00 00 0a 00 32 00 0a 00 22

					39 01 00 00 00 00 2b df 50 42 58 81 2d

					   00 00 00 00 00 00 6b 00 00 00 00 00

					   00 00 00 01 0f ff d4 0e 00 00 00 00

					   00 00 0f 53 f1 00 00 00 00 00 00 00

					   00

					39 01 00 00 00 00 02 f7 01

					39 01 00 00 00 00 02 b0 80

					39 01 00 00 00 00 0a e4 34 b4 00 00 00

					   39 04 09 34

					39 01 00 00 00 00 02 e6 00

					39 01 00 00 00 00 02 b0 04

					39 01 00 00 00 00 03 df 50 40

					39 01 00 00 00 00 06 f3 50 00 00 00 00

					39 01 00 00 00 00 02 f2 11
@@ -148,7 +219,11 @@ 
					39 01 00 00 00 00 05 2a 00 00 04 37

					39 01 00 00 00 00 05 2b 00 00 09 23

					05 01 00 00 78 00 01 11

					05 01 00 00 00 00 01 29

					05 01 00 00 14 00 01 29

					39 01 00 00 00 00 02 b0 00

					39 01 00 00 00 00 1a c2 09 24 0c 00 00

					   0c 03 14 00 09 3c 00 00 00 00 00 00

					   00 00 00 00 00 30 00 6c

				];



				qcom,mdss-dsi-off-command = [
@@ -245,7 +320,7 @@ 
					39 01 00 00 00 00 05 2a 00 00 04 37

					39 01 00 00 00 00 05 2b 00 00 09 23

					05 01 00 00 78 00 01 11

					05 01 00 00 00 00 01 29

					05 01 00 00 14 00 01 29

				];



				qcom,mdss-dsi-off-command = [

display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -22,6 +22,11 @@ 
		qcom,mdss-dsi-mdp-trigger = "none";

		qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;

		qcom,adjust-timer-wakeup-ms = <1>;

		qcom,mdss-dsi-panel-hdr-enabled;

		qcom,mdss-dsi-panel-hdr-color-primaries = < 14500 15500 32000

			17000 15500 30000 8000 3000>;

		qcom,mdss-dsi-panel-peak-brightness = <4200000>;

		qcom,mdss-dsi-panel-blackness-level = <3230>;

		qcom,mdss-dsi-display-timings {

			timing@0 {

				qcom,mdss-dsi-panel-width = <1080>;

display/lahaina-sde-common.dtsi

0 → 100644
+426 −0
Original line number Diff line number Diff line 
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>



&soc {

	mdss_mdp: qcom,mdss_mdp@ae00000 {

		compatible = "qcom,sde-kms";

		reg = <0x0ae00000 0x84000>,

		      <0x0aeb0000 0x2008>,

		      <0x0aeac000 0x800>;

		reg-names = "mdp_phys",

			"vbif_phys",

			"regdma_phys";



		clock-rate = <0 0 0 0 460000000 19200000 460000000 19200000>;

		clock-max-rate = <0 0 0 0 460000000 19200000 460000000

					460000000>;



		/* interrupt config */

		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-controller;

		#interrupt-cells = <1>;



		/* hw blocks */

		qcom,sde-off = <0x1000>;

		qcom,sde-len = <0x494>;



		qcom,sde-ctl-off = <0x16000 0x17000 0x18000

					0x19000 0x1a000 0x1b000>;

		qcom,sde-ctl-size = <0x1e8>;

		qcom,sde-ctl-display-pref = "primary", "none", "none",

			    "none", "none", "none";



		qcom,sde-mixer-off = <0x45000 0x46000 0x47000

				      0x48000 0x49000 0x4a000>;

		qcom,sde-mixer-size = <0x320>;

		qcom,sde-mixer-display-pref = "primary", "primary", "none",

					      "none", "none", "none";



		qcom,sde-mixer-cwb-pref = "none", "none", "cwb",

					      "cwb", "cwb", "cwb";



		qcom,sde-dspp-top-off = <0x1300>;

		qcom,sde-dspp-top-size = <0x80>;

		qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;

		qcom,sde-dspp-size = <0x1800>;



		qcom,sde-dspp-rc-version = <0x00010000>;

		qcom,sde-dspp-rc-off = <0x15800 0x14c00>;

		qcom,sde-dspp-rc-size = <0x100>;

		qcom,sde-dspp-rc-mem-size = <2720>;



		qcom,sde-dest-scaler-top-off = <0x00061000>;

		qcom,sde-dest-scaler-top-size = <0x1c>;

		qcom,sde-dest-scaler-off = <0x800 0x1000>;

		qcom,sde-dest-scaler-size = <0x800>;



		qcom,sde-wb-off = <0x66000>;

		qcom,sde-wb-size = <0x2c8>;

		qcom,sde-wb-xin-id = <6>;

		qcom,sde-wb-id = <2>;

		qcom,sde-wb-clk-ctrl = <0x2bc 16>;

		qcom,sde-wb-clk-status = <0x3bc 20>;



		qcom,sde-intf-off = <0x35000 0x36000

					0x37000 0x38000>;

		qcom,sde-intf-size = <0x2c0>;

		qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";

		qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>;



		qcom,sde-pp-off = <0x6a000 0x6b000

					0x6c000 0x6d000 0x6e000 0x6f000>;

		qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>;

		qcom,sde-pp-size = <0xd4>;

		qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>;



		qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000>;

		qcom,sde-merge-3d-size = <0x10>;



		qcom,sde-cdm-off = <0x7a200>;

		qcom,sde-cdm-size = <0x224>;



		qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>;

		qcom,sde-dsc-size = <0x10>;

		qcom,sde-dsc-pair-mask = <2 1 4 3>;

		qcom,sde-dsc-hw-rev = "dsc_1_2";

		qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>;

		qcom,sde-dsc-enc-size = <0x100>;

		qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>;

		qcom,sde-dsc-ctl-size = <0x10>;

		qcom,sde-dsc-native422-supp = <0 0 1 1>;

		qcom,sde-dsc-linewidth = <2048>;



		qcom,sde-dither-off = <0xe0 0xe0 0xe0

						0xe0 0xe0 0xe0>;

		qcom,sde-dither-version = <0x00020000>;

		qcom,sde-dither-size = <0x20>;



		qcom,sde-vdc-off = <0x7C000>;

		qcom,sde-vdc-size = <0x10>;

		qcom,sde-vdc-hw-rev = "vdc_1_2";

		qcom,sde-vdc-enc = <0x200>;

		qcom,sde-vdc-enc-size = <0x1C8>;

		qcom,sde-vdc-ctl = <0xf00>;

		qcom,sde-vdc-ctl-size = <0x10>;



		qcom,sde-sspp-type = "vig", "vig", "vig", "vig",

					"dma", "dma", "dma", "dma";



		qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000

					0x25000 0x27000 0x29000 0x2b000>;

		qcom,sde-sspp-src-size = <0x1f8>;



		qcom,sde-sspp-xin-id = <0 4 8 12

					1 5 9 13>;

		qcom,sde-sspp-excl-rect = <1 1 1 1

						1 1 1 1>;

		qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;

		qcom,sde-smart-dma-rev = "smart_dma_v2p5";



		qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>;



		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98

						0xb0 0xc8 0xe0 0xf8 0x110>;



		qcom,sde-max-per-pipe-bw-kbps = <3900000 3900000

						 3900000 3900000

						 3900000 3900000

						 3900000 3900000>;



		qcom,sde-max-per-pipe-bw-high-kbps = <5200000 5200000

						      5200000 5200000

						      5200000 5200000

						      5200000 5200000>;



		/* offsets are relative to "mdp_phys + qcom,sde-off */

		qcom,sde-sspp-clk-ctrl =

				<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,

				 <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;

		qcom,sde-sspp-clk-status =

				<0x2b0 0>, <0x2b8 0>, <0x2c0 0>, <0x2c8 0>,

				 <0x2b0 12>, <0x2b8 12>, <0x2c8 12>, <0x2c8 14>;

		qcom,sde-sspp-csc-off = <0x1a00>;

		qcom,sde-csc-type = "csc-10bit";

		qcom,sde-qseed-sw-lib-rev = "qseedv3lite";

		qcom,sde-qseed-scalar-version = <0x3000>;

		qcom,sde-sspp-qseed-off = <0xa00>;

		qcom,sde-mixer-linewidth = <2560>;

		qcom,sde-sspp-linewidth = <4096>;

		qcom,sde-wb-linewidth = <4096>;

		qcom,sde-wb-linewidth-linear = <5120>;

		qcom,sde-mixer-blendstages = <0xb>;

		qcom,sde-highest-bank-bit = <0x8 0x3>,

					    <0x7 0x2>;

		qcom,sde-ubwc-version = <0x400>;

		qcom,sde-ubwc-swizzle = <0x6>;

		qcom,sde-ubwc-bw-calc-version = <0x1>;

		qcom,sde-ubwc-static = <0x1>;

		qcom,sde-macrotile-mode = <0x1>;

		qcom,sde-smart-panel-align-mode = <0xc>;

		qcom,sde-panic-per-pipe;

		qcom,sde-has-cdp;

		qcom,sde-has-src-split;

		qcom,sde-pipe-order-version = <0x1>;

		qcom,sde-has-dim-layer;

		qcom,sde-has-dest-scaler;

		qcom,sde-max-trusted-vm-displays = <1>;



		qcom,sde-max-dest-scaler-input-linewidth = <2048>;

		qcom,sde-max-dest-scaler-output-linewidth = <2560>;

		qcom,sde-max-bw-low-kbps = <11800000>;

		qcom,sde-max-bw-high-kbps = <15500000>;

		qcom,sde-min-core-ib-kbps = <2500000>;

		qcom,sde-min-llcc-ib-kbps = <0>;

		qcom,sde-min-dram-ib-kbps = <800000>;

		qcom,sde-dram-channels = <2>;

		qcom,sde-num-nrt-paths = <0>;



		qcom,sde-dspp-spr-off = <0x15400 0x14400>;

		qcom,sde-dspp-spr-size = <0x200>;

		qcom,sde-dspp-spr-version = <0x00010000>;



		qcom,sde-dspp-demura-off = <0x15600 0x14800>;

		qcom,sde-dspp-demura-size = <0x200>;

		qcom,sde-dspp-demura-version = <0x00010000>;



		qcom,sde-uidle-off = <0x80000>;

		qcom,sde-uidle-size = <0x70>;



		qcom,sde-vbif-off = <0>;

		qcom,sde-vbif-size = <0x1040>;

		qcom,sde-vbif-id = <0>;

		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;

		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;



		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;

		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;

		qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;

		qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 6>;



		qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000

			0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff

			0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>;



		qcom,sde-safe-lut = <0xfff0 0xff00 0xffff 0x3ff 0xff00 0xff00>,

			<0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>;



		qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>;

		qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>;

		qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;

		qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;

		qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>;

		qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>;

		qcom,sde-qos-refresh-rates = <60 120>;



		qcom,sde-cdp-setting = <1 1>, <1 0>;



		qcom,sde-qos-cpu-mask = <0x3>;

		qcom,sde-qos-cpu-dma-latency = <300>;

		qcom,sde-qos-cpu-irq-latency = <300>;



		/* offsets are relative to "mdp_phys + qcom,sde-off */

		qcom,sde-reg-dma-off = <0 0x400>;

		qcom,sde-reg-dma-id = <0 1>;

		qcom,sde-reg-dma-version = <0x00020000>;

		qcom,sde-reg-dma-trigger-off = <0x119c>;

		qcom,sde-reg-dma-xin-id = <7>;

		qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;



		qcom,sde-secure-sid-mask = <0x4000821>;



		qcom,sde-reg-bus,vectors-KBps = <0 0>,

				<0 74000>,

				<0 148000>,

				<0 265000>;



		qcom,sde-sspp-vig-blocks {

			qcom,sde-vig-csc-off = <0x1a00>;

			qcom,sde-vig-qseed-off = <0xa00>;

			qcom,sde-vig-qseed-size = <0xa0>;

			qcom,sde-vig-gamut = <0x1d00 0x00060001>;

			qcom,sde-vig-igc = <0x1d00 0x00060000>;

			qcom,sde-vig-inverse-pma;

		};



		qcom,sde-sspp-dma-blocks {

			dgm@0 {

				qcom,sde-dma-igc = <0x400 0x00050000>;

				qcom,sde-dma-gc = <0x600 0x00050000>;

				qcom,sde-dma-inverse-pma;

				qcom,sde-dma-csc-off = <0x200>;

			};



			dgm@1 {

				qcom,sde-dma-igc = <0x1400 0x00050000>;

				qcom,sde-dma-gc = <0x600 0x00050000>;

				qcom,sde-dma-inverse-pma;

				qcom,sde-dma-csc-off = <0x1200>;

			};

		};



		qcom,sde-dspp-blocks {

			qcom,sde-dspp-igc = <0x1260 0x00040000>;

			qcom,sde-dspp-hsic = <0x800 0x00010007>;

			qcom,sde-dspp-memcolor = <0x880 0x00010007>;

			qcom,sde-dspp-hist = <0x800 0x00010007>;

			qcom,sde-dspp-sixzone= <0x900 0x00010007>;

			qcom,sde-dspp-vlut = <0xa00 0x00010008>;

			qcom,sde-dspp-gamut = <0x1000 0x00040003>;

			qcom,sde-dspp-pcc = <0x1700 0x00040000>;

			qcom,sde-dspp-gc = <0x17c0 0x00010008>;

			qcom,sde-dspp-dither = <0x82c 0x00010007>;

		};



	};



	mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {

		compatible = "qcom,dsi-ctrl-hw-v2.5";

		label = "dsi-ctrl-0";

		cell-index = <0>;

		frame-threshold-time-us = <800>;

		reg = <0xae94000 0x400>,

			<0xaf08000 0x4>;

		reg-names = "dsi_ctrl", "disp_cc_base";

		interrupt-parent = <&mdss_mdp>;

		interrupts = <4 0>;



		qcom,ctrl-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,ctrl-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p2";

				qcom,supply-min-voltage = <1200000>;

				qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <8350>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "refgen";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {

		compatible = "qcom,dsi-ctrl-hw-v2.5";

		label = "dsi-ctrl-1";

		cell-index = <1>;

		frame-threshold-time-us = <800>;

		reg = <0xae96000 0x400>,

			<0xaf08000 0x4>;

		reg-names = "dsi_ctrl", "disp_cc_base";

		interrupt-parent = <&mdss_mdp>;

		interrupts = <5 0>;



		qcom,ctrl-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,ctrl-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-1p2";

				qcom,supply-min-voltage = <1200000>;

				qcom,supply-max-voltage = <1200000>;

				qcom,supply-enable-load = <8350>;

				qcom,supply-disable-load = <0>;

			};

		};



		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "refgen";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 {

		compatible = "qcom,dsi-phy-v4.2";

		label = "dsi-phy-0";

		cell-index = <0>;

		#clock-cells = <1>;

		reg = <0xae94400 0x800>,

		      <0xae94900 0x27c>,

		      <0xaf03000 0x8>,

		      <0xae94200 0x100>;

		reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";

		pll-label = "dsi_pll_5nm";



		qcom,platform-strength-ctrl = [55 03

						55 03

						55 03

						55 03

						55 00];

		qcom,platform-lane-config = [00 00 0a 0a

						00 00 0a 0a

						00 00 0a 0a

						00 00 0a 0a

						00 00 8a 8a];

		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];

		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage = <880000>;

				qcom,supply-max-voltage = <880000>;

				qcom,supply-enable-load = <37550>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 {

		compatible = "qcom,dsi-phy-v4.2";

		label = "dsi-phy-1";

		cell-index = <1>;

		#clock-cells = <1>;

		reg = <0xae96400 0x800>,

		      <0xae96900 0x27c>,

		      <0xaf03000 0x8>,

		      <0xae96200 0x100>;

		reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";

		pll-label = "dsi_pll_5nm";



		qcom,platform-strength-ctrl = [55 03

						55 03

						55 03

						55 03

						55 00];

		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];

		qcom,platform-lane-config = [00 00 0a 0a

						00 00 0a 0a

						00 00 0a 0a

						00 00 0a 0a

						00 00 8a 8a];

		qcom,phy-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,phy-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "vdda-0p9";

				qcom,supply-min-voltage = <880000>;

				qcom,supply-max-voltage = <880000>;

				qcom,supply-enable-load = <37550>;

				qcom,supply-disable-load = <0>;

			};

		};

	};

};