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Commit f1e21273 authored by Vivek Aknurwar's avatar Vivek Aknurwar
Browse files

clk: qcom: clk-alpha-pll: Add support for controlling zonda5lpe PLL 



Add programming sequence support for managing the zonda 5lpe
PLL.

Change-Id: I6eaef174c42ff148503d37bdbe9ebbabd7f65238
Signed-off-by: default avatarVivek Aknurwar <viveka@codeaurora.org>
parent 3817fdb8

drivers/clk/qcom/clk-alpha-pll.c

+183 −25
Original line number Diff line number Diff line
@@ -163,6 +163,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 
		[PLL_OFF_OPMODE] = 0x38,

		[PLL_OFF_ALPHA_VAL] = 0x40,

	},

	[CLK_ALPHA_PLL_TYPE_ZONDA_5LPE] = {

		[PLL_OFF_L_VAL] = 0x04,

		[PLL_OFF_ALPHA_VAL] = 0x08,

		[PLL_OFF_USER_CTL] = 0x0c,

		[PLL_OFF_CONFIG_CTL] = 0x10,

		[PLL_OFF_CONFIG_CTL_U] = 0x14,

		[PLL_OFF_CONFIG_CTL_U1] = 0x18,

		[PLL_OFF_TEST_CTL] = 0x1c,

		[PLL_OFF_TEST_CTL_U] = 0x20,

		[PLL_OFF_TEST_CTL_U1] = 0x24,

		[PLL_OFF_OPMODE] = 0x28,

		[PLL_OFF_STATUS] = 0x38,

	},

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@@ -199,6 +212,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 
#define ZONDA_PLL_OUT_MASK		0xF

#define ZONDA_STAY_IN_CFA		BIT(16)

#define ZONDA_PLL_FREQ_LOCK_DET	BIT(29)

#define ZONDA_5LPE_ENABLE_VOTE_RUN	BIT(21)



#define TRION_PLL_STANDBY	0x0

#define TRION_PLL_RUN		0x1
@@ -941,84 +955,104 @@ static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate, 
	return clamp(rate, min_freq, max_freq);

}



static int clk_zonda_pll_is_enabled(struct clk_hw *hw)

static int __zonda_pll_is_enabled(struct clk_alpha_pll *pll,

					struct regmap *regmap)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 mode_regval, opmode_regval;

	int ret;



	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode_regval);

	if (ret)

		return ret;

	ret = regmap_read(pll->clkr.regmap, PLL_OPMODE(pll), &opmode_regval);

	if (ret)

	ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);

	ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);

	if (ret) {

		pr_err("zonda pll is enabled reg read failed\n");

		return ret;

	}



	return ((opmode_regval & PLL_OPMODE_RUN) &&

		(mode_regval & PLL_OUTCTRL));

}



static int clk_zonda_pll_is_enabled(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);



	return (opmode_regval & PLL_OPMODE_RUN) &&

		(mode_regval & PLL_OUTCTRL);

	return __zonda_pll_is_enabled(pll, pll->clkr.regmap);

}



void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

int clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config)

{

	int ret;



	ret = __zonda_pll_is_enabled(pll, regmap);

	if (ret < 0)

		return ret;

	else if (ret) {

		pr_warn("%s PLL is already enabled\n",

				clk_hw_get_name(&pll->clkr.hw));

		return 0;

	}



	if (config->l)

		regmap_write(regmap, PLL_L_VAL(pll), config->l);

		ret |= regmap_write(regmap, PLL_L_VAL(pll), config->l);



	if (config->alpha)

		regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);

		ret |= regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);



	if (config->config_ctl_val)

		regmap_write(regmap, PLL_CONFIG_CTL(pll),

		ret |= regmap_write(regmap, PLL_CONFIG_CTL(pll),

				config->config_ctl_val);



	if (config->config_ctl_hi_val)

		regmap_write(regmap, PLL_CONFIG_CTL_U(pll),

		ret |= regmap_write(regmap, PLL_CONFIG_CTL_U(pll),

				config->config_ctl_hi_val);



	if (config->config_ctl_hi1_val)

		regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),

		ret |= regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),

				config->config_ctl_hi1_val);



	if (config->user_ctl_val)

		regmap_write(regmap, PLL_USER_CTL(pll),

		ret |= regmap_write(regmap, PLL_USER_CTL(pll),

				config->user_ctl_val);



	if (config->user_ctl_hi_val)

		regmap_write(regmap, PLL_USER_CTL_U(pll),

		ret |= regmap_write(regmap, PLL_USER_CTL_U(pll),

				config->user_ctl_hi_val);



	if (config->user_ctl_hi1_val)

		regmap_write(regmap, PLL_USER_CTL_U1(pll),

		ret |= regmap_write(regmap, PLL_USER_CTL_U1(pll),

				config->user_ctl_hi1_val);



	if (config->test_ctl_val)

		regmap_write(regmap, PLL_TEST_CTL(pll),

		ret |= regmap_write(regmap, PLL_TEST_CTL(pll),

				config->test_ctl_val);



	if (config->test_ctl_hi_val)

		regmap_write(regmap, PLL_TEST_CTL_U(pll),

		ret |= regmap_write(regmap, PLL_TEST_CTL_U(pll),

				config->test_ctl_hi_val);



	if (config->test_ctl_hi1_val)

		regmap_write(regmap, PLL_TEST_CTL_U1(pll),

		ret |= regmap_write(regmap, PLL_TEST_CTL_U1(pll),

				config->test_ctl_hi1_val);



	regmap_update_bits(regmap, PLL_MODE(pll),

	ret |= regmap_update_bits(regmap, PLL_MODE(pll),

			 PLL_BYPASSNL, 0);



	/* Disable PLL output */

	regmap_update_bits(regmap, PLL_MODE(pll),

	ret |= regmap_update_bits(regmap, PLL_MODE(pll),

			 PLL_OUTCTRL, 0);



	/* Set operation mode to OFF */

	regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);

	ret |= regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);



	/* PLL should be in OFF mode before continuing */

	wmb();



	/* Place the PLL in STANDBY mode */

	regmap_update_bits(regmap, PLL_MODE(pll),

	ret |= regmap_update_bits(regmap, PLL_MODE(pll),

				 PLL_RESET_N, PLL_RESET_N);



	return ret ? -EIO : 0;

}



static int clk_zonda_pll_enable(struct clk_hw *hw)
@@ -1185,6 +1219,120 @@ clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_BITWIDTH);

}



int clk_zonda_5lpe_pll_configure(struct clk_alpha_pll *pll,

		struct regmap *regmap,

		const struct alpha_pll_config *config)

{

	return clk_zonda_pll_configure(pll, regmap, config);

}

EXPORT_SYMBOL(clk_zonda_5lpe_pll_configure);





static int clk_zonda_5lpe_pll_enable(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 val, test_ctl_val;

	int ret;



	ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);

	if (ret)

		return ret;



	/* If in FSM mode, just vote for it */

	if (val & ZONDA_5LPE_ENABLE_VOTE_RUN) {

		ret = clk_enable_regmap(hw);

		if (ret)

			return ret;

		return wait_for_pll_enable_active(pll);

	}



	/* Check if PLL is already enabled */

	ret = __zonda_pll_is_enabled(pll, pll->clkr.regmap);

	if (ret < 0)

		return ret;

	else if (ret) {

		pr_warn("%s PLL is already enabled\n",

				clk_hw_get_name(&pll->clkr.hw));

		return 0;

	}



	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

						 PLL_RESET_N | PLL_BYPASSNL,

						 PLL_RESET_N | PLL_BYPASSNL);

	if (ret)

		return ret;



	/* Set operation mode to RUN */

	regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_OPMODE_RUN);



	ret = regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);

	if (ret)

		return ret;



	/* If cfa mode then poll for freq lock */

	if (test_ctl_val & ZONDA_STAY_IN_CFA)

		ret = wait_for_zonda_pll_freq_lock(pll);

	else

		ret = wait_for_pll_enable_lock(pll);

	if (ret)

		return ret;



	/* Enable the PLL outputs */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),

				ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);

	if (ret)

		return ret;



	/* Enable the global PLL outputs */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

				 PLL_OUTCTRL, PLL_OUTCTRL);

	if (ret)

		return ret;



	/* Ensure that the write above goes through before returning. */

	mb();



	return ret;

}



static void clk_zonda_5lpe_pll_disable(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 val, mask;

	int ret;



	ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);

	if (ret)

		return;



	/* If in FSM mode, just unvote it */

	if (val & ZONDA_5LPE_ENABLE_VOTE_RUN) {

		clk_disable_regmap(hw);

		return;

	}



	/* Disable the global PLL output */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

							PLL_OUTCTRL, 0);

	if (ret)

		return;



	/* Disable the PLL outputs */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),

			PLL_OUT_MASK, 0);

	if (ret)

		return;



	/* Place the PLL mode in STANDBY */

	regmap_write(pll->clkr.regmap, PLL_OPMODE(pll),

			PLL_OPMODE_STANDBY);



	mask = PLL_RESET_N | PLL_BYPASSNL;

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);

	if (ret)

		return;

}



const struct clk_ops clk_alpha_pll_ops = {

	.enable = clk_alpha_pll_enable,

	.disable = clk_alpha_pll_disable,
@@ -1234,6 +1382,16 @@ const struct clk_ops clk_alpha_pll_zonda_ops = { 
};

EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);



const struct clk_ops clk_alpha_pll_zonda_5lpe_ops = {

	.enable = clk_zonda_5lpe_pll_enable,

	.disable = clk_zonda_5lpe_pll_disable,

	.is_enabled = clk_zonda_pll_is_enabled,

	.recalc_rate = clk_zonda_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_zonda_pll_set_rate,

};

EXPORT_SYMBOL(clk_alpha_pll_zonda_5lpe_ops);



static unsigned long

clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)

{

drivers/clk/qcom/clk-alpha-pll.h

+6 −2
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ enum { 
	CLK_ALPHA_PLL_TYPE_LUCID,

	CLK_ALPHA_PLL_TYPE_ZONDA,

	CLK_ALPHA_PLL_TYPE_LUCID_5LPE,

	CLK_ALPHA_PLL_TYPE_ZONDA_5LPE,

	CLK_ALPHA_PLL_TYPE_MAX,

};
@@ -141,6 +142,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; 


extern const struct clk_ops clk_alpha_pll_zonda_ops;

extern const struct clk_ops clk_alpha_pll_postdiv_zonda_ops;

extern const struct clk_ops clk_alpha_pll_zonda_5lpe_ops;



extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;

extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
@@ -155,10 +157,12 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
				const struct alpha_pll_config *config);

void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config);

void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

int clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config);

int clk_lucid_5lpe_pll_configure(struct clk_alpha_pll *pll,

				struct regmap *regmap,

				const struct alpha_pll_config *config);



int clk_zonda_5lpe_pll_configure(struct clk_alpha_pll *pll,

				struct regmap *regmap,

				const struct alpha_pll_config *config);

#endif