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Commit f18145e8 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: Add L3 snoop bw device on Lahaina"

parents 3764cbcb 8b77828d

qcom/shima.dtsi

+39 −0
Original line number Diff line number Diff line
@@ -2305,6 +2305,28 @@ 
		qcom,count-unit = <0x10000>;

	};



	snoop_l3_bw: qcom,snoop-l3-bw {

		compatible = "qcom,devfreq-icc-l3bw";

		reg = <0x18590100 0xa0>;

		reg-names = "ftbl-base";

		qcom,bus-width = <32>;

		governor = "bw_hwmon";

		interconnects =

			<&epss_l3_cpu MASTER_EPSS_L3_APPS

			 &epss_l3_cpu SLAVE_EPSS_L3_SHARED>;

	};



	snoop_l3_bwmon: qcom,snoop-l3-bwmon@9091000 {

		compatible = "qcom,bimc-bwmon4";

		reg = <0x90b9100 0x300>, <0x90b9000 0x200>;

		reg-names = "base", "global_base";

		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;

		qcom,mport = <0>;

		qcom,hw-timer-hz = <19200000>;

		qcom,target-dev = <&snoop_l3_bw>;

		qcom,count-unit = <0x10000>;

	};



	cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {

		compatible = "qcom,devfreq-icc-l3";

		reg = <0x18590100 0xa0>;
@@ -2466,6 +2488,13 @@ 
		mboxes = <&qmp_aop 0>;

	};



	cpu7_cpu_ddr_qoslatfloor: qcom,cpu7-cpu-ddr-qoslatfloor {

		compatible = "qcom,devfreq-qoslat";

		governor = "mem_latency";

		operating-points-v2 = <&qoslat_opp_table>;

		mboxes = <&qmp_aop 0>;

	};



	cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {

		qcom,core-dev-table =

			<  300000  300000000 >,
@@ -2735,6 +2764,16 @@ 
				<  300000 1 >,

				< 3000000 2 >;

		};



		cpu7_qoslatmon: qcom,cpu7-qoslatmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU7>;

			qcom,target-dev = <&cpu7_cpu_ddr_qoslatfloor>;

			qcom,cachemiss-ev = <0x1000>;

			qcom,core-dev-table =

				< 2169600 1 >,

				< 2707200 2 >;

		};

	};



	qcom,sps {