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Commit f1487c19 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Simon Horman
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arm64: dts: renesas: r8a77970: add thermal support 



Describe THS/CIVM in the R8A77970 device tree.

Based on the original (and large) patches by Vladimir Barinov.

Signed-off-by: default avatarVladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 85170420

arch/arm64/boot/dts/renesas/r8a77970.dtsi

+32 −0
Original line number Original line Diff line number Diff line
@@ -300,6 +300,19 @@ 
			#power-domain-cells = <1>;

			#power-domain-cells = <1>;

		};

		};





		thermal: thermal@e6190000 {

			compatible = "renesas,thermal-r8a77970";

			reg =  <0 0xe6190000 0 0x10

				0 0xe6190100 0 0x120>;

			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 522>;

			power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;

			resets = <&cpg 522>;

			#thermal-sensor-cells = <0>;

		};



		intc_ex: interrupt-controller@e61c0000 {

		intc_ex: interrupt-controller@e61c0000 {

			compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";

			compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";

			#interrupt-cells = <2>;

			#interrupt-cells = <2>;
@@ -1033,6 +1046,25 @@ 
		};

		};

	};

	};





	thermal-zones {

		cpu-thermal {

			polling-delay-passive = <250>;

			polling-delay = <1000>;

			thermal-sensors = <&thermal>;



			trips {

				cpu-crit {

					temperature = <120000>;

					hysteresis = <2000>;

					type = "critical";

				};

			};



			cooling-maps {

			};

		};

	};



	timer {

	timer {

		compatible = "arm,armv8-timer";

		compatible = "arm,armv8-timer";

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,

		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,