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Commit f126df85 authored by Iyappan Subramanian's avatar Iyappan Subramanian Committed by David S. Miller
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drivers: net: xgene: fix: Coalescing values for v2 hardware 



Changing the interrupt trigger region id to 2 and the
corresponding threshold set0/set1 values to 8/16.

Signed-off-by: default avatarIyappan Subramanian <isubramanian@apm.com>
Signed-off-by: default avatarToan Le <toanle@apm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent b5a4a3eb

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

+2 −0
Original line number Diff line number Diff line
@@ -55,8 +55,10 @@ enum xgene_enet_rm { 
#define PREFETCH_BUF_EN		BIT(21)

#define CSR_RING_ID_BUF		0x000c

#define CSR_PBM_COAL		0x0014

#define CSR_PBM_CTICK0		0x0018

#define CSR_PBM_CTICK1		0x001c

#define CSR_PBM_CTICK2		0x0020

#define CSR_PBM_CTICK3		0x0024

#define CSR_THRESHOLD0_SET1	0x0030

#define CSR_THRESHOLD1_SET1	0x0034

#define CSR_RING_NE_INT_MODE	0x017c

drivers/net/ethernet/apm/xgene/xgene_enet_ring2.c

+7 −5
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring) 
		ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK);

		ring_cfg[3] |= SET_BIT(X2_DEQINTEN);

	}

	ring_cfg[0] |= SET_VAL(X2_CFGCRID, 1);

	ring_cfg[0] |= SET_VAL(X2_CFGCRID, 2);



	addr >>= 8;

	ring_cfg[2] |= QCOHERENT | SET_VAL(RINGADDRL, addr);
@@ -192,13 +192,15 @@ static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring) 


static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring)

{

	u32 data = 0x7777;

	u32 data = 0x77777777;



	xgene_enet_ring_wr32(ring, CSR_PBM_COAL, 0x8e);

	xgene_enet_ring_wr32(ring, CSR_PBM_CTICK0, data);

	xgene_enet_ring_wr32(ring, CSR_PBM_CTICK1, data);

	xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data << 16);

	xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x40);

	xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x80);

	xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data);

	xgene_enet_ring_wr32(ring, CSR_PBM_CTICK3, data);

	xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x08);

	xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x10);

}



struct xgene_ring_ops xgene_ring2_ops = {