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Commit f0e4a063 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Move GEM domain management to its own file 



Continuing the decluttering of i915_gem.c, that of the read/write
domains, perhaps the biggest of GEM's follies?

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190528092956.14910-7-chris@chris-wilson.co.uk
parent b414fcd5

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -87,6 +87,7 @@ i915-y += $(gt-y) 
# GEM (Graphics Execution Management) code

obj-y += gem/

gem-y += \

	gem/i915_gem_domain.o \

	gem/i915_gem_object.o \

	gem/i915_gem_mman.o \

	gem/i915_gem_pages.o \

drivers/gpu/drm/i915/gem/i915_gem_domain.c

0 → 100644
+782 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/i915/gem/i915_gem_object.h

+29 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ 


#include "i915_gem_object_types.h"



#include "i915_gem_gtt.h"



void i915_gem_init__objects(struct drm_i915_private *i915);



struct drm_i915_gem_object *i915_gem_object_alloc(void);
@@ -358,6 +360,20 @@ void 
i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,

				   unsigned int flush_domains);



int i915_gem_object_prepare_read(struct drm_i915_gem_object *obj,

				 unsigned int *needs_clflush);

int i915_gem_object_prepare_write(struct drm_i915_gem_object *obj,

				  unsigned int *needs_clflush);

#define CLFLUSH_BEFORE	BIT(0)

#define CLFLUSH_AFTER	BIT(1)

#define CLFLUSH_FLAGS	(CLFLUSH_BEFORE | CLFLUSH_AFTER)



static inline void

i915_gem_object_finish_access(struct drm_i915_gem_object *obj)

{

	i915_gem_object_unpin_pages(obj);

}



static inline struct intel_engine_cs *

i915_gem_object_last_write_engine(struct drm_i915_gem_object *obj)

{
@@ -379,6 +395,19 @@ void i915_gem_object_set_cache_coherency(struct drm_i915_gem_object *obj, 
					 unsigned int cache_level);

void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj);



int __must_check

i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);

int __must_check

i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);

int __must_check

i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);

struct i915_vma * __must_check

i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,

				     u32 alignment,

				     const struct i915_ggtt_view *view,

				     unsigned int flags);

void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);



static inline bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)

{

	if (obj->cache_dirty)

drivers/gpu/drm/i915/gvt/cmd_parser.c

+2 −2
Original line number Diff line number Diff line
@@ -1764,7 +1764,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) 
		goto err_free_bb;

	}



	ret = i915_gem_obj_prepare_shmem_write(bb->obj, &bb->clflush);

	ret = i915_gem_object_prepare_write(bb->obj, &bb->clflush);

	if (ret)

		goto err_free_obj;
@@ -1813,7 +1813,7 @@ static int perform_bb_shadow(struct parser_exec_state *s) 
err_unmap:

	i915_gem_object_unpin_map(bb->obj);

err_finish_shmem_access:

	i915_gem_obj_finish_shmem_access(bb->obj);

	i915_gem_object_finish_access(bb->obj);

err_free_obj:

	i915_gem_object_put(bb->obj);

err_free_bb:

drivers/gpu/drm/i915/gvt/scheduler.c

+3 −3
Original line number Diff line number Diff line
@@ -482,7 +482,7 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) 
						bb->obj->base.size);

				bb->clflush &= ~CLFLUSH_AFTER;

			}

			i915_gem_obj_finish_shmem_access(bb->obj);

			i915_gem_object_finish_access(bb->obj);

			bb->accessing = false;



		} else {
@@ -510,7 +510,7 @@ static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) 
			if (ret)

				goto err;



			i915_gem_obj_finish_shmem_access(bb->obj);

			i915_gem_object_finish_access(bb->obj);

			bb->accessing = false;



			ret = i915_vma_move_to_active(bb->vma,
@@ -588,7 +588,7 @@ static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload) 
	list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {

		if (bb->obj) {

			if (bb->accessing)

				i915_gem_obj_finish_shmem_access(bb->obj);

				i915_gem_object_finish_access(bb->obj);



			if (bb->va && !IS_ERR(bb->va))

				i915_gem_object_unpin_map(bb->obj);