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Commit f0d2f68a authored by Tero Kristo's avatar Tero Kristo Committed by Paul Walmsley
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ARM: OMAP3: clock: use clk_features flags for omap3 DPLL4 checks 



DPLL4 can't be reprogrammed on OMAP3430 ES1.0 due to hardware limitation.
Currently, the code does runtime omap_rev() check to see the chip it is
being executed on, instead, change this to use clk_features flags.
This avoids need for runtime omap_rev() checks.

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent f114040e

arch/arm/mach-omap2/clock.c

+4 −0
Original line number Diff line number Diff line
@@ -771,4 +771,8 @@ void __init ti_clk_init_features(void) 
		ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;

	else if (cpu_is_omap34xx())

		ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;



	/* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */

	if (omap_rev() == OMAP3430_REV_ES1_0)

		ti_clk_features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;

}

arch/arm/mach-omap2/clock.h

+1 −0
Original line number Diff line number Diff line
@@ -234,6 +234,7 @@ struct ti_clk_features { 
};



#define TI_CLK_DPLL_HAS_FREQSEL		(1 << 0)

#define TI_CLK_DPLL4_DENY_REPROGRAM	(1 << 1)



extern struct ti_clk_features ti_clk_features;

arch/arm/mach-omap2/clock3xxx.c

+1 −1
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate, 
	 * on 3430ES1 prevents us from changing DPLL multipliers or dividers

	 * on DPLL4.

	 */

	if (omap_rev() == OMAP3430_REV_ES1_0) {

	if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {

		pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");

		return -EINVAL;

	}