Loading qcom/lahaina.dtsi +24 −0 Original line number Diff line number Diff line Loading @@ -613,6 +613,30 @@ #reset-cells = <1>; }; clock_apsscc: syscon@182a0000 { compatible = "syscon"; reg = <0x182a0000 0x1c>; }; clock_mccc: syscon@90ba000 { compatible = "syscon"; reg = <0x90ba000 0x54>; }; clock_debugcc: qcom,cc-debug { compatible = "qcom,lahaina-debugcc"; qcom,gcc = <&clock_gcc>; qcom,videocc = <&clock_videocc>; qcom,dispcc = <&clock_dispcc>; qcom,camcc = <&clock_camcc>; qcom,gpucc = <&clock_gpucc>; qcom,apsscc = <&clock_apsscc>; qcom,mccc = <&clock_mccc>; clock-names = "xo_clk_src"; clocks = <&clock_rpmh RPMH_CXO_CLK>; #clock-cells = <1>; }; /* CAM_CC GDSCs */ cam_cc_bps_gdsc: qcom,gdsc@ad07004 { compatible = "qcom,gdsc"; Loading Loading
qcom/lahaina.dtsi +24 −0 Original line number Diff line number Diff line Loading @@ -613,6 +613,30 @@ #reset-cells = <1>; }; clock_apsscc: syscon@182a0000 { compatible = "syscon"; reg = <0x182a0000 0x1c>; }; clock_mccc: syscon@90ba000 { compatible = "syscon"; reg = <0x90ba000 0x54>; }; clock_debugcc: qcom,cc-debug { compatible = "qcom,lahaina-debugcc"; qcom,gcc = <&clock_gcc>; qcom,videocc = <&clock_videocc>; qcom,dispcc = <&clock_dispcc>; qcom,camcc = <&clock_camcc>; qcom,gpucc = <&clock_gpucc>; qcom,apsscc = <&clock_apsscc>; qcom,mccc = <&clock_mccc>; clock-names = "xo_clk_src"; clocks = <&clock_rpmh RPMH_CXO_CLK>; #clock-cells = <1>; }; /* CAM_CC GDSCs */ cam_cc_bps_gdsc: qcom,gdsc@ad07004 { compatible = "qcom,gdsc"; Loading