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Commit f0c8ac80 authored by Kumar Gala's avatar Kumar Gala
Browse files

[POWERPC] DTS cleanup 



Removed the following cruft from .dts files:
* 32-bit in cpu node -- doesn't exist in any spec and not used by kernel
* removed built-in (chrp legacy)
* Removed #interrupt-cells in places they don't need to be set
* Fixed ranges on lite5200*
* Removed clock-frequency from i8259 pic node, not sure where this came from
* Removed big-endian from i8259 pic nodes, this was just bogus

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 5d54ddcb

arch/powerpc/boot/dts/holly.dts

+0 −1
Original line number Diff line number Diff line
@@ -31,7 +31,6 @@ 
			timebase-frequency = <2faf080>;

			clock-frequency = <23c34600>;

			bus-frequency = <bebc200>;

			32-bit;

		};

	};

arch/powerpc/boot/dts/kuroboxHD.dts

+0 −2
Original line number Diff line number Diff line
@@ -47,7 +47,6 @@ XXXX add flash parts, rtc, ?? 
	soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */

		#address-cells = <1>;

		#size-cells = <1>;

		#interrupt-cells = <2>;

		device_type = "soc";

		compatible = "mpc10x";

		store-gathering = <0>; /* 0 == off, !0 == on */
@@ -101,7 +100,6 @@ XXXX add flash parts, rtc, ?? 
			compatible = "chrp,open-pic";

			interrupt-controller;

			reg = <80040000 40000>;

			built-in;

		};



		pci@fec00000 {

arch/powerpc/boot/dts/kuroboxHG.dts

+0 −2
Original line number Diff line number Diff line
@@ -47,7 +47,6 @@ XXXX add flash parts, rtc, ?? 
	soc10x { /* AFAICT need to make soc for 8245's uarts to be defined */

		#address-cells = <1>;

		#size-cells = <1>;

		#interrupt-cells = <2>;

		device_type = "soc";

		compatible = "mpc10x";

		store-gathering = <0>; /* 0 == off, !0 == on */
@@ -101,7 +100,6 @@ XXXX add flash parts, rtc, ?? 
			compatible = "chrp,open-pic";

			interrupt-controller;

			reg = <80040000 40000>;

			built-in;

		};



		pci@fec00000 {

arch/powerpc/boot/dts/lite5200.dts

+2 −5
Original line number Diff line number Diff line
@@ -37,7 +37,6 @@ 
			timebase-frequency = <0>;	// from bootloader

			bus-frequency = <0>;		// from bootloader

			clock-frequency = <0>;		// from bootloader

			32-bit;

		};

	};
@@ -50,10 +49,9 @@ 
		model = "fsl,mpc5200";

		compatible = "mpc5200";

		revision = "";			// from bootloader

		#interrupt-cells = <3>;

		device_type = "soc";

		ranges = <0 f0000000 f0010000>;

		reg = <f0000000 00010000>;

		ranges = <0 f0000000 0000c000>;

		reg = <f0000000 00000100>;

		bus-frequency = <0>;		// from bootloader

		system-frequency = <0>;		// from bootloader
@@ -69,7 +67,6 @@ 
			device_type = "interrupt-controller";

			compatible = "mpc5200-pic";

			reg = <500 80>;

			built-in;

		};



		gpt@600 {	// General Purpose Timer

arch/powerpc/boot/dts/lite5200b.dts

+2 −5
Original line number Diff line number Diff line
@@ -37,7 +37,6 @@ 
			timebase-frequency = <0>;	// from bootloader

			bus-frequency = <0>;		// from bootloader

			clock-frequency = <0>;		// from bootloader

			32-bit;

		};

	};
@@ -50,10 +49,9 @@ 
		model = "fsl,mpc5200b";

		compatible = "mpc5200";

		revision = "";			// from bootloader

		#interrupt-cells = <3>;

		device_type = "soc";

		ranges = <0 f0000000 f0010000>;

		reg = <f0000000 00010000>;

		ranges = <0 f0000000 0000c000>;

		reg = <f0000000 00000100>;

		bus-frequency = <0>;		// from bootloader

		system-frequency = <0>;		// from bootloader
@@ -69,7 +67,6 @@ 
			device_type = "interrupt-controller";

			compatible = "mpc5200b-pic\0mpc5200-pic";

			reg = <500 80>;

			built-in;

		};



		gpt@600 {	// General Purpose Timer