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Commit f0553ba0 authored by Frederick Lawler's avatar Frederick Lawler Committed by Bjorn Helgaas
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PCI/AER: Use cached AER Capability offset 



Replace pci_find_ext_capability(..., PCI_EXT_CAP_ID_ERR) calls with
pci_dev->aer_cap.

pci_dev->aer_cap is initialized in pci_init_capabilities(), which happens
before any of these users of the AER Capability.

Signed-off-by: default avatarFrederick Lawler <fred@fredlawl.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent d850882b

drivers/pci/pcie/aer/aer_inject.c

+2 −2
Original line number Diff line number Diff line
@@ -344,7 +344,7 @@ static int aer_inject(struct aer_error_inj *einj) 
		goto out_put;

	}



	pos_cap_err = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);

	pos_cap_err = dev->aer_cap;

	if (!pos_cap_err) {

		pci_err(dev, "aer_inject: Device doesn't support AER\n");

		ret = -EPROTONOSUPPORT;
@@ -355,7 +355,7 @@ static int aer_inject(struct aer_error_inj *einj) 
	pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,

			      &uncor_mask);



	rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR);

	rp_pos_cap_err = rpdev->aer_cap;

	if (!rp_pos_cap_err) {

		pci_err(rpdev, "aer_inject: Root port doesn't support AER\n");

		ret = -EPROTONOSUPPORT;

drivers/pci/pcie/aer/ecrc.c

+2 −2
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ static int enable_ecrc_checking(struct pci_dev *dev) 
	if (!pci_is_pcie(dev))

		return -ENODEV;



	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);

	pos = dev->aer_cap;

	if (!pos)

		return -ENODEV;
@@ -68,7 +68,7 @@ static int disable_ecrc_checking(struct pci_dev *dev) 
	if (!pci_is_pcie(dev))

		return -ENODEV;



	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);

	pos = dev->aer_cap;

	if (!pos)

		return -ENODEV;

drivers/pci/pcie/portdrv_core.c

+10 −4
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ static void release_pcie_device(struct device *dev) 
static int pcie_message_numbers(struct pci_dev *dev, int mask,

				u32 *pme, u32 *aer, u32 *dpc)

{

	u32 nvec = 0, pos, reg32;

	u32 nvec = 0, pos;

	u16 reg16;



	/*
@@ -56,8 +56,11 @@ static int pcie_message_numbers(struct pci_dev *dev, int mask, 
		nvec = *pme + 1;

	}



#ifdef CONFIG_PCIEAER

	if (mask & PCIE_PORT_SERVICE_AER) {

		pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);

		u32 reg32;



		pos = dev->aer_cap;

		if (pos) {

			pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS,

					      &reg32);
@@ -65,6 +68,7 @@ static int pcie_message_numbers(struct pci_dev *dev, int mask, 
			nvec = max(nvec, *aer + 1);

		}

	}

#endif



	if (mask & PCIE_PORT_SERVICE_DPC) {

		pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
@@ -207,8 +211,9 @@ static int get_port_device_capability(struct pci_dev *dev) 
			  PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);

	}



	if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR) &&

	    pci_aer_available() && (pcie_ports_native || host->native_aer)) {

#ifdef CONFIG_PCIEAER

	if (dev->aer_cap && pci_aer_available() &&

	    (pcie_ports_native || host->native_aer)) {

		services |= PCIE_PORT_SERVICE_AER;



		/*
@@ -217,6 +222,7 @@ static int get_port_device_capability(struct pci_dev *dev) 
		 */

		pci_disable_pcie_error_reporting(dev);

	}

#endif



	/*

	 * Root ports are capable of generating PME too.  Root Complex