Merge "msm: kgsl: Re-define maximum number of cmds for hwscheduling" (f0421cce) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/msm/adreno.c

+16 −10

Original line number	Diff line number	Diff line
		@@ -3062,26 +3062,32 @@ int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,
		* was successful
		*/
		if (!(status & fence_mask))
		return 0;
		break;

		/* Wait a small amount of time before trying again */
		udelay(GMU_CORE_WAKEUP_DELAY_US);

		/* Try to write the fenced register again */
		adreno_writereg(adreno_dev, offset, val);
		}

		if (i < GMU_CORE_SHORT_WAKEUP_RETRY_LIMIT)
		return 0;

		if (i == GMU_CORE_SHORT_WAKEUP_RETRY_LIMIT)
		if (i == GMU_CORE_LONG_WAKEUP_RETRY_LIMIT) {
		dev_err(adreno_dev->dev.dev,
		"Waited %d usecs to write fenced register 0x%x. Continuing to wait...\n",
		(GMU_CORE_SHORT_WAKEUP_RETRY_LIMIT *
		GMU_CORE_WAKEUP_DELAY_US),
		"Timed out waiting %d usecs to write fenced register 0x%x\n",
		i * GMU_CORE_WAKEUP_DELAY_US,
		reg_offset);
		return -ETIMEDOUT;
		}

		dev_err(adreno_dev->dev.dev,
		"Timed out waiting %d usecs to write fenced register 0x%x\n",
		GMU_CORE_LONG_WAKEUP_RETRY_LIMIT * GMU_CORE_WAKEUP_DELAY_US,
		"Waited %d usecs to write fenced register 0x%x\n",
		i * GMU_CORE_WAKEUP_DELAY_US,
		reg_offset);
		return -ETIMEDOUT;

		return 0;
		}

		bool adreno_is_cx_dbgc_register(struct kgsl_device *device,

+6 −0

Original line number	Diff line number	Diff line
		@@ -120,6 +120,12 @@ void a6xx_hwsched_snapshot(struct adreno_device *adreno_dev,
		snapshot, adreno_snapshot_global,
		entry->gpu_md);

		if (entry->desc.mem_kind == MEMKIND_PROFILE)
		kgsl_snapshot_add_section(device,
		KGSL_SNAPSHOT_SECTION_GPU_OBJECT_V2,
		snapshot, adreno_snapshot_global,
		entry->gpu_md);

		if (entry->desc.mem_kind == MEMKIND_CSW_SMMU_INFO)
		kgsl_snapshot_add_section(device,
		KGSL_SNAPSHOT_SECTION_GPU_OBJECT_V2,

+5 −0

Original line number	Diff line number	Diff line
		@@ -6,6 +6,11 @@
		#ifndef _ADRENO_A6XX_HWSCHED_HFI_H_
		#define _ADRENO_A6XX_HWSCHED_HFI_H_

		/* Maximum number of IBs in a submission */
		#define HWSCHED_MAX_NUMIBS \
		((HFI_MAX_MSG_SIZE - offsetof(struct hfi_issue_cmd_cmd, ibs)) \
		/ sizeof(struct hfi_issue_ib))

		enum mem_kind {
		/** @MEMKIND_GENERIC: Used for requesting generic memory */
		MEMKIND_GENERIC = 0,

+17 −0

Original line number	Diff line number	Diff line
		@@ -836,6 +836,23 @@ int adreno_hwsched_queue_cmds(struct kgsl_device_private *dev_priv,
		if (!count)
		return -EINVAL;

		for (i = 0; i < count; i++) {
		struct kgsl_drawobj_cmd *cmdobj;
		struct kgsl_memobj_node *ib;
		u32 numibs = 0;

		if (drawobj[i]->type != CMDOBJ_TYPE)
		continue;

		cmdobj = CMDOBJ(drawobj[i]);

		list_for_each_entry(ib, &cmdobj->cmdlist, node)
		numibs++;

		if (numibs > HWSCHED_MAX_NUMIBS)
		return -EINVAL;
		}

		ret = _check_context_state(&drawctxt->base);
		if (ret)
		return ret;

+4 −0

Original line number	Diff line number	Diff line
		@@ -854,6 +854,10 @@ void adreno_snapshot(struct kgsl_device device, struct kgsl_snapshot snapshot,
		snapshot, adreno_snapshot_global,
		adreno_dev->pwron_fixup);

		kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_GPU_OBJECT_V2,
		snapshot, adreno_snapshot_global,
		adreno_dev->profile_buffer);

		if (kgsl_mmu_get_mmutype(device) == KGSL_MMU_TYPE_IOMMU)
		adreno_snapshot_iommu(device, snapshot);