Merge "msm: kgsl: Always boot GMU with default CM3 config" (efe21f42) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/msm/adreno.c

+5 −3

Original line number	Diff line number	Diff line
		@@ -324,6 +324,7 @@ void adreno_fault_detect_stop(struct adreno_device *adreno_dev)
		/* Send an NMI to the GMU */
		void adreno_gmu_send_nmi(struct adreno_device *adreno_dev)
		{
		u32 val;
		/* Mask so there's no interrupt caused by NMI */
		adreno_write_gmureg(adreno_dev,
		ADRENO_REG_GMU_GMU2HOST_INTR_MASK, 0xFFFFFFFF);
		@@ -333,9 +334,10 @@ void adreno_gmu_send_nmi(struct adreno_device *adreno_dev)
		if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG))
		adreno_write_gmureg(adreno_dev,
		ADRENO_REG_GMU_NMI_CONTROL_STATUS, 0);
		adreno_write_gmureg(adreno_dev,
		ADRENO_REG_GMU_CM3_CFG,
		(1 << GMU_CM3_CFG_NONMASKINTR_SHIFT));

		adreno_read_gmureg(adreno_dev, ADRENO_REG_GMU_CM3_CFG, &val);
		val \|= 1 << GMU_CM3_CFG_NONMASKINTR_SHIFT;
		adreno_write_gmureg(adreno_dev, ADRENO_REG_GMU_CM3_CFG, val);

		/* Make sure the NMI is invoked before we proceed*/
		wmb();

+11 −0

Original line number	Diff line number	Diff line
		@@ -357,6 +357,10 @@ static int a6xx_gmu_start(struct kgsl_device *device)

		/* Bring GMU out of reset */
		gmu_core_regwrite(device, A6XX_GMU_CM3_SYSRESET, 0);

		/* Make sure the write is posted before moving ahead */
		wmb();

		if (timed_poll_check(device,
		A6XX_GMU_CM3_FW_INIT_RESULT,
		val, GMU_START_TIMEOUT, mask)) {
		@@ -1058,6 +1062,13 @@ static int a6xx_gmu_fw_start(struct kgsl_device *device,
		gmu_core_regwrite(device, A6XX_GMU_AHB_FENCE_RANGE_0,
		GMU_FENCE_RANGE_MASK);

		/*
		* Make sure that CM3 state is at reset value. Snapshot is changing
		* NMI bit and if we boot up GMU with NMI bit set GMU will boot
		* straight in to NMI handler without executing __main code
		*/
		gmu_core_regwrite(device, A6XX_GMU_CM3_CFG, 0x4052);

		/* Pass chipid to GMU FW, must happen before starting GMU */

		/* Keep Core and Major bitfields unchanged */