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Commit efb05a50 authored by Manu Gautam's avatar Manu Gautam Committed by Kishon Vijay Abraham I
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phy: qcom-qmp: Add support for QMP V3 USB3 PHY 



QMP V3 USB3 PHY is a DisplayPort (DP) and USB combo PHY
with dual RX/TX lanes to support type-c. There is a
separate block DP_COM for configuration related to type-c
or DP. Add support for dp_com region and secondary rx/tx
lanes initialization.

Signed-off-by: default avatarManu Gautam <mgautam@codeaurora.org>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 8587b220

drivers/phy/qualcomm/phy-qcom-qmp.c

+220 −3
Original line number Diff line number Diff line
@@ -47,6 +47,21 @@ 
/* QPHY_COM_PCS_READY_STATUS bit */

#define PCS_READY				BIT(0)



/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */

/* DP PHY soft reset */

#define SW_DPPHY_RESET				BIT(0)

/* mux to select DP PHY reset control, 0:HW control, 1: software reset */

#define SW_DPPHY_RESET_MUX			BIT(1)

/* USB3 PHY soft reset */

#define SW_USB3PHY_RESET			BIT(2)

/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */

#define SW_USB3PHY_RESET_MUX			BIT(3)



/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */

#define USB3_MODE				BIT(0) /* enables USB3 mode */

#define DP_MODE					BIT(1) /* enables DP mode */





#define PHY_INIT_COMPLETE_TIMEOUT		1000

#define POWER_DOWN_DELAY_US_MIN			10

#define POWER_DOWN_DELAY_US_MAX			11
@@ -122,6 +137,12 @@ static const unsigned int usb3phy_regs_layout[] = { 
	[QPHY_PCS_READY_STATUS]		= 0x17c,

};



static const unsigned int qmp_v3_usb3phy_regs_layout[] = {

	[QPHY_SW_RESET]			= 0x00,

	[QPHY_START_CTRL]		= 0x08,

	[QPHY_PCS_READY_STATUS]		= 0x174,

};



static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),

	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
@@ -350,6 +371,112 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 
	QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),

};



static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),

};



static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),

};



static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),

};



static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {

	/* FLL settings */

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),



	/* Lock Det settings */

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),



	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),



	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),

};



/* struct qmp_phy_cfg - per-PHY initialization config */

struct qmp_phy_cfg {

	/* phy-type - PCIE/UFS/USB */
@@ -394,6 +521,12 @@ struct qmp_phy_cfg { 
	/* power_down delay in usec */

	int pwrdn_delay_min;

	int pwrdn_delay_max;



	/* true, if PHY has a separate DP_COM control block */

	bool has_phy_dp_com_ctrl;

	/* Register offset of secondary tx/rx lanes for USB DP combo PHY */

	unsigned int tx_b_lane_offset;

	unsigned int rx_b_lane_offset;

};



/**
@@ -424,6 +557,7 @@ struct qmp_phy { 
 *

 * @dev: device

 * @serdes: iomapped memory space for phy's serdes

 * @dp_com: iomapped memory space for phy's dp_com control block

 *

 * @clks: array of clocks required by phy

 * @resets: array of resets required by phy
@@ -437,6 +571,7 @@ struct qmp_phy { 
struct qcom_qmp {

	struct device *dev;

	void __iomem *serdes;

	void __iomem *dp_com;



	struct clk_bulk_data *clks;

	struct reset_control **resets;
@@ -478,6 +613,10 @@ static const char * const msm8996_phy_clk_l[] = { 
	"aux", "cfg_ahb", "ref",

};



static const char * const qmp_v3_phy_clk_l[] = {

	"aux", "cfg_ahb", "ref", "com_aux",

};



/* list of resets */

static const char * const msm8996_pciephy_reset_l[] = {

	"phy", "common", "cfg",
@@ -584,6 +723,38 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 
	.pwrdn_delay_max	= 1005,		/* us */

};



static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {

	.type			= PHY_TYPE_USB3,

	.nlanes			= 1,



	.serdes_tbl		= qmp_v3_usb3_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),

	.tx_tbl			= qmp_v3_usb3_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_tx_tbl),

	.rx_tbl			= qmp_v3_usb3_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_rx_tbl),

	.pcs_tbl		= qmp_v3_usb3_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),

	.clk_list		= qmp_v3_phy_clk_l,

	.num_clks		= ARRAY_SIZE(qmp_v3_phy_clk_l),

	.reset_list		= msm8996_usb3phy_reset_l,

	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),

	.vreg_list		= msm8996_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(msm8996_phy_vreg_l),

	.regs			= qmp_v3_usb3phy_regs_layout,



	.start_ctrl		= SERDES_START | PCS_START,

	.pwrdn_ctrl		= SW_PWRDN,

	.mask_pcs_ready		= PHYSTATUS,



	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,

	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,



	.has_phy_dp_com_ctrl	= true,

	.tx_b_lane_offset	= 0x400,

	.rx_b_lane_offset	= 0x400,

};



static void qcom_qmp_phy_configure(void __iomem *base,

				   const unsigned int *regs,

				   const struct qmp_phy_init_tbl tbl[],
@@ -620,6 +791,7 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp) 
{

	const struct qmp_phy_cfg *cfg = qmp->cfg;

	void __iomem *serdes = qmp->serdes;

	void __iomem *dp_com = qmp->dp_com;

	int ret, i;



	mutex_lock(&qmp->phy_mutex);
@@ -663,6 +835,23 @@ static int qcom_qmp_phy_com_init(struct qcom_qmp *qmp) 
		qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],

			     SW_PWRDN);



	if (cfg->has_phy_dp_com_ctrl) {

		qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,

			     SW_PWRDN);

		/* override hardware control for reset of qmp phy */

		qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,

			     SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |

			     SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);



		qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,

			     USB3_MODE | DP_MODE);



		/* bring both QMP USB and QMP DP PHYs PCS block out of reset */

		qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,

			     SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |

			     SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);

	}



	/* Serdes configuration */

	qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,

			       cfg->serdes_tbl_num);
@@ -746,6 +935,7 @@ static int qcom_qmp_phy_init(struct phy *phy) 
	void __iomem *tx = qphy->tx;

	void __iomem *rx = qphy->rx;

	void __iomem *pcs = qphy->pcs;

	void __iomem *dp_com = qmp->dp_com;

	void __iomem *status;

	unsigned int mask, val;

	int ret;
@@ -767,7 +957,16 @@ static int qcom_qmp_phy_init(struct phy *phy) 


	/* Tx, Rx, and PCS configurations */

	qcom_qmp_phy_configure(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num);

	/* Configuration for other LANE for USB-DP combo PHY */

	if (cfg->has_phy_dp_com_ctrl)

		qcom_qmp_phy_configure(tx + cfg->tx_b_lane_offset, cfg->regs,

				       cfg->tx_tbl, cfg->tx_tbl_num);



	qcom_qmp_phy_configure(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num);

	if (cfg->has_phy_dp_com_ctrl)

		qcom_qmp_phy_configure(rx + cfg->rx_b_lane_offset, cfg->regs,

				       cfg->rx_tbl, cfg->rx_tbl_num);



	qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);



	/*
@@ -781,6 +980,8 @@ static int qcom_qmp_phy_init(struct phy *phy) 


	/* Pull PHY out of reset state */

	qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);

	if (cfg->has_phy_dp_com_ctrl)

		qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);



	/* start SerDes and Phy-Coding-Sublayer */

	qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
@@ -1031,6 +1232,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { 
	}, {

		.compatible = "qcom,ipq8074-qmp-pcie-phy",

		.data = &ipq8074_pciephy_cfg,

	}, {

		.compatible = "qcom,qmp-v3-usb3-phy",

		.data = &qmp_v3_usb3phy_cfg,

	},

	{ },

};
@@ -1054,6 +1258,11 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) 
	qmp->dev = dev;

	dev_set_drvdata(dev, qmp);



	/* Get the specific init parameters of QMP phy */

	qmp->cfg = of_device_get_match_data(dev);

	if (!qmp->cfg)

		return -EINVAL;



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	base = devm_ioremap_resource(dev, res);

	if (IS_ERR(base))
@@ -1062,10 +1271,18 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) 
	/* per PHY serdes; usually located at base address */

	qmp->serdes = base;



	mutex_init(&qmp->phy_mutex);

	/* per PHY dp_com; if PHY has dp_com control block */

	if (qmp->cfg->has_phy_dp_com_ctrl) {

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

						   "dp_com");

		base = devm_ioremap_resource(dev, res);

		if (IS_ERR(base))

			return PTR_ERR(base);



	/* Get the specific init parameters of QMP phy */

	qmp->cfg = of_device_get_match_data(dev);

		qmp->dp_com = base;

	}



	mutex_init(&qmp->phy_mutex);



	ret = qcom_qmp_phy_clk_init(dev);

	if (ret)