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Commit ef335b80 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: ep-pcie: Give BAR0 and BAR2 the right size"

parents 03fb5fd7 7149f891

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+0 −1
Original line number Diff line number Diff line
@@ -330,7 +330,6 @@ struct ep_pcie_dev_t { 
	struct ep_pcie_irq_info_t    irq[EP_PCIE_MAX_IRQ];

	struct ep_pcie_res_info_t    res[EP_PCIE_MAX_RES];



	u32			     mmio_res_size;

	void __iomem                 *parf;

	void __iomem                 *phy;

	void __iomem                 *mmio;

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+5 −4
Original line number Diff line number Diff line
@@ -529,16 +529,18 @@ static void ep_pcie_pipe_clk_deinit(struct ep_pcie_dev_t *dev) 


static void ep_pcie_bar_init(struct ep_pcie_dev_t *dev)

{

	struct resource *res = dev->res[EP_PCIE_RES_MMIO].resource;

	u32 mask = res->end - res->start;

	u32 properties = 0x4;



	EP_PCIE_DBG(dev, "PCIe V%d: BAR mask to program is 0x%x\n",

			dev->rev, dev->mmio_res_size);

			dev->rev, mask);



	/* Configure BAR mask via CS2 */

	ep_pcie_write_mask(dev->elbi + PCIE20_ELBI_CS2_ENABLE, 0, BIT(0));

	ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0, dev->mmio_res_size);

	ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0, mask);

	ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x4, 0);

	ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x8, dev->mmio_res_size);

	ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x8, mask);

	ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0xc, 0);

	ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x10, 0);

	ep_pcie_write_reg(dev->dm_core, PCIE20_BAR0 + 0x14, 0);
@@ -1300,7 +1302,6 @@ static int ep_pcie_get_resources(struct ep_pcie_dev_t *dev, 
					goto out;

				}

			}

			dev->mmio_res_size = res->end = res->start;

		} else {

			EP_PCIE_DBG(dev, "start addr for %s is %pa\n",

				res_info->name,	&res->start);