Loading include/asm-mips/war.h +0 −1 Original line number Diff line number Diff line Loading @@ -188,7 +188,6 @@ #define ICACHE_REFILLS_WORKAROUND_WAR 1 #endif /* * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. Loading Loading
include/asm-mips/war.h +0 −1 Original line number Diff line number Diff line Loading @@ -188,7 +188,6 @@ #define ICACHE_REFILLS_WORKAROUND_WAR 1 #endif /* * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. Loading
Ralf Baechle <ralf@linux-mips.org>Ralf Baechle <ralf@linux-mips.org>