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Commit eec26555 authored by Tony Lindgren's avatar Tony Lindgren
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bus: ti-sysc: Enable interconnect target module autoidle bit on enable 



For interconnect target modules with autoidle bit wired, we need to manage
it for enable and disable.

Tested-by: default avatarKeerthy <j-keerthy@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent bd808f9a

drivers/bus/ti-sysc.c

+12 −1
Original line number Diff line number Diff line
@@ -893,7 +893,7 @@ static int sysc_enable_module(struct device *dev) 
	/* Set MIDLE mode */

	idlemodes = ddata->cfg.midlemodes;

	if (!idlemodes || regbits->midle_shift < 0)

		return 0;

		goto set_autoidle;



	best_mode = fls(ddata->cfg.midlemodes) - 1;

	if (best_mode > SYSC_IDLE_MASK) {
@@ -905,6 +905,14 @@ static int sysc_enable_module(struct device *dev) 
	reg |= best_mode << regbits->midle_shift;

	sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);



set_autoidle:

	/* Autoidle bit must enabled separately if available */

	if (regbits->autoidle_shift >= 0 &&

	    ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {

		reg |= 1 << regbits->autoidle_shift;

		sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);

	}



	return 0;

}
@@ -966,6 +974,9 @@ static int sysc_disable_module(struct device *dev) 


	reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);

	reg |= best_mode << regbits->sidle_shift;

	if (regbits->autoidle_shift >= 0 &&

	    ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))

		reg |= 1 << regbits->autoidle_shift;

	sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);



	return 0;