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Commit ee5789db authored by Robert Richter's avatar Robert Richter Committed by Ingo Molnar
Browse files

perf, x86: Share IBS macros between perf and oprofile 



Moving IBS macros from oprofile to <asm/perf_event.h> to make it
available to perf. No additional changes.

Signed-off-by: default avatarRobert Richter <robert.richter@amd.com>
Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1316597423-25723-2-git-send-email-robert.richter@amd.com


Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent efc3aac5

arch/x86/include/asm/perf_event.h

+35 −3
Original line number Original line Diff line number Diff line
@@ -46,6 +46,9 @@ 
#define AMD64_RAW_EVENT_MASK		\

#define AMD64_RAW_EVENT_MASK		\

	(X86_RAW_EVENT_MASK          |  \

	(X86_RAW_EVENT_MASK          |  \

	 AMD64_EVENTSEL_EVENT)

	 AMD64_EVENTSEL_EVENT)

#define AMD64_NUM_COUNTERS				4

#define AMD64_NUM_COUNTERS_F15H				6

#define AMD64_NUM_COUNTERS_MAX				AMD64_NUM_COUNTERS_F15H





#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL		0x3c

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)

#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK		(0x00 << 8)
@@ -113,6 +116,35 @@ union cpuid10_edx { 
 */

 */

#define X86_PMC_IDX_FIXED_BTS				(X86_PMC_IDX_FIXED + 16)

#define X86_PMC_IDX_FIXED_BTS				(X86_PMC_IDX_FIXED + 16)





/*

 * IBS cpuid feature detection

 */



#define IBS_CPUID_FEATURES		0x8000001b



/*

 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but

 * bit 0 is used to indicate the existence of IBS.

 */

#define IBS_CAPS_AVAIL			(1U<<0)

#define IBS_CAPS_FETCHSAM		(1U<<1)

#define IBS_CAPS_OPSAM			(1U<<2)

#define IBS_CAPS_RDWROPCNT		(1U<<3)

#define IBS_CAPS_OPCNT			(1U<<4)

#define IBS_CAPS_BRNTRGT		(1U<<5)

#define IBS_CAPS_OPCNTEXT		(1U<<6)



#define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\

					 | IBS_CAPS_FETCHSAM	\

					 | IBS_CAPS_OPSAM)



/*

 * IBS APIC setup

 */

#define IBSCTL				0x1cc

#define IBSCTL_LVT_OFFSET_VALID		(1ULL<<8)

#define IBSCTL_LVT_OFFSET_MASK		0x0F



/* IbsFetchCtl bits/masks */

/* IbsFetchCtl bits/masks */

#define IBS_FETCH_RAND_EN	(1ULL<<57)

#define IBS_FETCH_RAND_EN	(1ULL<<57)

#define IBS_FETCH_VAL		(1ULL<<49)

#define IBS_FETCH_VAL		(1ULL<<49)

arch/x86/kernel/cpu/perf_event_amd.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -411,7 +411,7 @@ static __initconst const struct x86_pmu amd_pmu = { 
	.perfctr		= MSR_K7_PERFCTR0,

	.perfctr		= MSR_K7_PERFCTR0,

	.event_map		= amd_pmu_event_map,

	.event_map		= amd_pmu_event_map,

	.max_events		= ARRAY_SIZE(amd_perfmon_event_map),

	.max_events		= ARRAY_SIZE(amd_perfmon_event_map),

	.num_counters		= 4,

	.num_counters		= AMD64_NUM_COUNTERS,

	.cntval_bits		= 48,

	.cntval_bits		= 48,

	.cntval_mask		= (1ULL << 48) - 1,

	.cntval_mask		= (1ULL << 48) - 1,

	.apic			= 1,

	.apic			= 1,
@@ -575,7 +575,7 @@ static __initconst const struct x86_pmu amd_pmu_f15h = { 
	.perfctr		= MSR_F15H_PERF_CTR,

	.perfctr		= MSR_F15H_PERF_CTR,

	.event_map		= amd_pmu_event_map,

	.event_map		= amd_pmu_event_map,

	.max_events		= ARRAY_SIZE(amd_perfmon_event_map),

	.max_events		= ARRAY_SIZE(amd_perfmon_event_map),

	.num_counters		= 6,

	.num_counters		= AMD64_NUM_COUNTERS_F15H,

	.cntval_bits		= 48,

	.cntval_bits		= 48,

	.cntval_mask		= (1ULL << 48) - 1,

	.cntval_mask		= (1ULL << 48) - 1,

	.apic			= 1,

	.apic			= 1,

arch/x86/oprofile/op_model_amd.c

+3 −34
Original line number Original line Diff line number Diff line
@@ -29,8 +29,6 @@ 
#include "op_x86_model.h"

#include "op_x86_model.h"

#include "op_counter.h"

#include "op_counter.h"





#define NUM_COUNTERS		4

#define NUM_COUNTERS_F15H	6

#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX

#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX

#define NUM_VIRT_COUNTERS	32

#define NUM_VIRT_COUNTERS	32

#else

#else
@@ -69,35 +67,6 @@ struct ibs_state { 
static struct ibs_config ibs_config;

static struct ibs_config ibs_config;

static struct ibs_state ibs_state;

static struct ibs_state ibs_state;





/*

 * IBS cpuid feature detection

 */



#define IBS_CPUID_FEATURES		0x8000001b



/*

 * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but

 * bit 0 is used to indicate the existence of IBS.

 */

#define IBS_CAPS_AVAIL			(1U<<0)

#define IBS_CAPS_FETCHSAM		(1U<<1)

#define IBS_CAPS_OPSAM			(1U<<2)

#define IBS_CAPS_RDWROPCNT		(1U<<3)

#define IBS_CAPS_OPCNT			(1U<<4)

#define IBS_CAPS_BRNTRGT		(1U<<5)

#define IBS_CAPS_OPCNTEXT		(1U<<6)



#define IBS_CAPS_DEFAULT		(IBS_CAPS_AVAIL		\

					 | IBS_CAPS_FETCHSAM	\

					 | IBS_CAPS_OPSAM)



/*

 * IBS APIC setup

 */

#define IBSCTL				0x1cc

#define IBSCTL_LVT_OFFSET_VALID		(1ULL<<8)

#define IBSCTL_LVT_OFFSET_MASK		0x0F



/*

/*

 * IBS randomization macros

 * IBS randomization macros

 */

 */
@@ -439,7 +408,7 @@ static int op_amd_fill_in_addresses(struct op_msrs * const msrs) 
			goto fail;

			goto fail;

		}

		}

		/* both registers must be reserved */

		/* both registers must be reserved */

		if (num_counters == NUM_COUNTERS_F15H) {

		if (num_counters == AMD64_NUM_COUNTERS_F15H) {

			msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1);

			msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1);

			msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1);

			msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1);

		} else {

		} else {
@@ -741,9 +710,9 @@ static int op_amd_init(struct oprofile_operations *ops) 
	ops->create_files = setup_ibs_files;

	ops->create_files = setup_ibs_files;





	if (boot_cpu_data.x86 == 0x15) {

	if (boot_cpu_data.x86 == 0x15) {

		num_counters = NUM_COUNTERS_F15H;

		num_counters = AMD64_NUM_COUNTERS_F15H;

	} else {

	} else {

		num_counters = NUM_COUNTERS;

		num_counters = AMD64_NUM_COUNTERS;

	}

	}





	op_amd_spec.num_counters = num_counters;

	op_amd_spec.num_counters = num_counters;