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Commit ee3bb8c0 authored by Vivek Aknurwar's avatar Vivek Aknurwar
Browse files

clk: dt-bindings: gcc: Add USB PIPE clocks 



Update header file for usb pipe clock constants.

Change-Id: I459339210549e3f42c6ac0e578f6e9ffb5c5d1df
Signed-off-by: default avatarVivek Aknurwar <viveka@codeaurora.org>
parent 3817fdb8

include/dt-bindings/clock/qcom,gcc-lahaina.h

+192 −185
Original line number Diff line number Diff line
@@ -6,192 +6,199 @@ 
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_LAHAINA_H

#define _DT_BINDINGS_CLK_QCOM_GCC_LAHAINA_H



/* GCC HW clocks */

#define CORE_BI_PLL_TEST_SE					0

#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK			1

#define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK			2



/* GCC clocks */

#define GCC_AGGRE_NOC_PCIE_TBU_CLK				0

#define GCC_AGGRE_UFS_CARD_AXI_CLK				1

#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK			2

#define GCC_AGGRE_UFS_PHY_AXI_CLK				3

#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			4

#define GCC_AGGRE_USB3_PRIM_AXI_CLK				5

#define GCC_AGGRE_USB3_SEC_AXI_CLK				6

#define GCC_BOOT_ROM_AHB_CLK					7

#define GCC_CAMERA_AHB_CLK					8

#define GCC_CAMERA_HF_AXI_CLK					9

#define GCC_CAMERA_SF_AXI_CLK					10

#define GCC_CAMERA_XO_CLK					11

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				12

#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				13

#define GCC_CPUSS_AHB_CLK					14

#define GCC_CPUSS_AHB_CLK_SRC					15

#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC				16

#define GCC_DDRSS_GPU_AXI_CLK					17

#define GCC_DDRSS_PCIE_SF_TBU_CLK				18

#define GCC_DISP_AHB_CLK					19

#define GCC_DISP_HF_AXI_CLK					20

#define GCC_DISP_SF_AXI_CLK					21

#define GCC_DISP_XO_CLK						22

#define GCC_GP1_CLK						23

#define GCC_GP1_CLK_SRC						24

#define GCC_GP2_CLK						25

#define GCC_GP2_CLK_SRC						26

#define GCC_GP3_CLK						27

#define GCC_GP3_CLK_SRC						28

#define GCC_GPLL0						29

#define GCC_GPLL0_OUT_EVEN					30

#define GCC_GPLL4						31

#define GCC_GPLL9						32

#define GCC_GPU_CFG_AHB_CLK					33

#define GCC_GPU_GPLL0_CLK_SRC					34

#define GCC_GPU_GPLL0_DIV_CLK_SRC				35

#define GCC_GPU_IREF_EN						36

#define GCC_GPU_MEMNOC_GFX_CLK					37

#define GCC_GPU_SNOC_DVM_GFX_CLK				38

#define GCC_PCIE0_PHY_RCHNG_CLK					39

#define GCC_PCIE1_PHY_RCHNG_CLK					40

#define GCC_PCIE_0_AUX_CLK					41

#define GCC_PCIE_0_AUX_CLK_SRC					42

#define GCC_PCIE_0_CFG_AHB_CLK					43

#define GCC_PCIE_0_CLKREF_EN					44

#define GCC_PCIE_0_MSTR_AXI_CLK					45

#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				46

#define GCC_PCIE_0_PIPE_CLK					47

#define GCC_PCIE_0_SLV_AXI_CLK					48

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				49

#define GCC_PCIE_1_AUX_CLK					50

#define GCC_PCIE_1_AUX_CLK_SRC					51

#define GCC_PCIE_1_CFG_AHB_CLK					52

#define GCC_PCIE_1_CLKREF_EN					53

#define GCC_PCIE_1_MSTR_AXI_CLK					54

#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				55

#define GCC_PCIE_1_PIPE_CLK					56

#define GCC_PCIE_1_SLV_AXI_CLK					57

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				58

#define GCC_PDM2_CLK						59

#define GCC_PDM2_CLK_SRC					60

#define GCC_PDM_AHB_CLK						61

#define GCC_PDM_XO4_CLK						62

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				63

#define GCC_QMIP_CAMERA_RT_AHB_CLK				64

#define GCC_QMIP_DISP_AHB_CLK					65

#define GCC_QMIP_VIDEO_CVP_AHB_CLK				66

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				67

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				68

#define GCC_QUPV3_WRAP0_CORE_CLK				69

#define GCC_QUPV3_WRAP0_S0_CLK					70

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				71

#define GCC_QUPV3_WRAP0_S1_CLK					72

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				73

#define GCC_QUPV3_WRAP0_S2_CLK					74

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				75

#define GCC_QUPV3_WRAP0_S3_CLK					76

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				77

#define GCC_QUPV3_WRAP0_S4_CLK					78

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				79

#define GCC_QUPV3_WRAP0_S5_CLK					80

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				81

#define GCC_QUPV3_WRAP0_S6_CLK					82

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				83

#define GCC_QUPV3_WRAP0_S7_CLK					84

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				85

#define GCC_QUPV3_WRAP1_CORE_2X_CLK				86

#define GCC_QUPV3_WRAP1_CORE_CLK				87

#define GCC_QUPV3_WRAP1_S0_CLK					88

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				89

#define GCC_QUPV3_WRAP1_S1_CLK					90

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				91

#define GCC_QUPV3_WRAP1_S2_CLK					92

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				93

#define GCC_QUPV3_WRAP1_S3_CLK					94

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				95

#define GCC_QUPV3_WRAP1_S4_CLK					96

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				97

#define GCC_QUPV3_WRAP1_S5_CLK					98

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				99

#define GCC_QUPV3_WRAP2_CORE_2X_CLK				100

#define GCC_QUPV3_WRAP2_CORE_CLK				101

#define GCC_QUPV3_WRAP2_S0_CLK					102

#define GCC_QUPV3_WRAP2_S0_CLK_SRC				103

#define GCC_QUPV3_WRAP2_S1_CLK					104

#define GCC_QUPV3_WRAP2_S1_CLK_SRC				105

#define GCC_QUPV3_WRAP2_S2_CLK					106

#define GCC_QUPV3_WRAP2_S2_CLK_SRC				107

#define GCC_QUPV3_WRAP2_S3_CLK					108

#define GCC_QUPV3_WRAP2_S3_CLK_SRC				109

#define GCC_QUPV3_WRAP2_S4_CLK					110

#define GCC_QUPV3_WRAP2_S4_CLK_SRC				111

#define GCC_QUPV3_WRAP2_S5_CLK					112

#define GCC_QUPV3_WRAP2_S5_CLK_SRC				113

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				114

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				115

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				116

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				117

#define GCC_QUPV3_WRAP_2_M_AHB_CLK				118

#define GCC_QUPV3_WRAP_2_S_AHB_CLK				119

#define GCC_SDCC2_AHB_CLK					120

#define GCC_SDCC2_APPS_CLK					121

#define GCC_SDCC2_APPS_CLK_SRC					122

#define GCC_SDCC4_AHB_CLK					123

#define GCC_SDCC4_APPS_CLK					124

#define GCC_SDCC4_APPS_CLK_SRC					125

#define GCC_SYS_NOC_CPUSS_AHB_CLK				126

#define GCC_UFS_1_CLKREF_EN					127

#define GCC_UFS_CARD_AHB_CLK					128

#define GCC_UFS_CARD_AXI_CLK					129

#define GCC_UFS_CARD_AXI_CLK_SRC				130

#define GCC_UFS_CARD_AXI_HW_CTL_CLK				131

#define GCC_UFS_CARD_ICE_CORE_CLK				132

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				133

#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			134

#define GCC_UFS_CARD_PHY_AUX_CLK				135

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				136

#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				137

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				138

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				139

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				140

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				141

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			142

#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			143

#define GCC_UFS_PHY_AHB_CLK					144

#define GCC_UFS_PHY_AXI_CLK					145

#define GCC_UFS_PHY_AXI_CLK_SRC					146

#define GCC_UFS_PHY_AXI_HW_CTL_CLK				147

#define GCC_UFS_PHY_ICE_CORE_CLK				148

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				149

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				150

#define GCC_UFS_PHY_PHY_AUX_CLK					151

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				152

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				153

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				154

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				155

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				156

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				157

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				158

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			159

#define GCC_USB30_PRIM_MASTER_CLK				160

#define GCC_USB30_PRIM_MASTER_CLK_SRC				161

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				162

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			163

#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		164

#define GCC_USB30_PRIM_SLEEP_CLK				165

#define GCC_USB30_SEC_MASTER_CLK				166

#define GCC_USB30_SEC_MASTER_CLK_SRC				167

#define GCC_USB30_SEC_MOCK_UTMI_CLK				168

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				169

#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC			170

#define GCC_USB30_SEC_SLEEP_CLK					171

#define GCC_USB3_PRIM_PHY_AUX_CLK				172

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				173

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				174

#define GCC_USB3_PRIM_PHY_PIPE_CLK				175

#define GCC_USB3_SEC_CLKREF_EN					176

#define GCC_USB3_SEC_PHY_AUX_CLK				177

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				178

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				179

#define GCC_USB3_SEC_PHY_PIPE_CLK				180

#define GCC_VIDEO_AHB_CLK					181

#define GCC_VIDEO_AXI0_CLK					182

#define GCC_VIDEO_AXI1_CLK					183

#define GCC_VIDEO_XO_CLK					184

#define GCC_AGGRE_NOC_PCIE_TBU_CLK				3

#define GCC_AGGRE_UFS_CARD_AXI_CLK				4

#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK			5

#define GCC_AGGRE_UFS_PHY_AXI_CLK				6

#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			7

#define GCC_AGGRE_USB3_PRIM_AXI_CLK				8

#define GCC_AGGRE_USB3_SEC_AXI_CLK				9

#define GCC_BOOT_ROM_AHB_CLK					10

#define GCC_CAMERA_AHB_CLK					11

#define GCC_CAMERA_HF_AXI_CLK					12

#define GCC_CAMERA_SF_AXI_CLK					13

#define GCC_CAMERA_XO_CLK					14

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				15

#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				16

#define GCC_CPUSS_AHB_CLK					17

#define GCC_CPUSS_AHB_CLK_SRC					18

#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC				19

#define GCC_DDRSS_GPU_AXI_CLK					20

#define GCC_DDRSS_PCIE_SF_TBU_CLK				21

#define GCC_DISP_AHB_CLK					22

#define GCC_DISP_HF_AXI_CLK					23

#define GCC_DISP_SF_AXI_CLK					24

#define GCC_DISP_XO_CLK						25

#define GCC_GP1_CLK						26

#define GCC_GP1_CLK_SRC						27

#define GCC_GP2_CLK						28

#define GCC_GP2_CLK_SRC						29

#define GCC_GP3_CLK						30

#define GCC_GP3_CLK_SRC						31

#define GCC_GPLL0						32

#define GCC_GPLL0_OUT_EVEN					33

#define GCC_GPLL4						34

#define GCC_GPLL9						35

#define GCC_GPU_CFG_AHB_CLK					36

#define GCC_GPU_GPLL0_CLK_SRC					37

#define GCC_GPU_GPLL0_DIV_CLK_SRC				38

#define GCC_GPU_IREF_EN						39

#define GCC_GPU_MEMNOC_GFX_CLK					40

#define GCC_GPU_SNOC_DVM_GFX_CLK				41

#define GCC_PCIE0_PHY_RCHNG_CLK					42

#define GCC_PCIE1_PHY_RCHNG_CLK					43

#define GCC_PCIE_0_AUX_CLK					44

#define GCC_PCIE_0_AUX_CLK_SRC					45

#define GCC_PCIE_0_CFG_AHB_CLK					46

#define GCC_PCIE_0_CLKREF_EN					47

#define GCC_PCIE_0_MSTR_AXI_CLK					48

#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				49

#define GCC_PCIE_0_PIPE_CLK					50

#define GCC_PCIE_0_SLV_AXI_CLK					51

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				52

#define GCC_PCIE_1_AUX_CLK					53

#define GCC_PCIE_1_AUX_CLK_SRC					54

#define GCC_PCIE_1_CFG_AHB_CLK					55

#define GCC_PCIE_1_CLKREF_EN					56

#define GCC_PCIE_1_MSTR_AXI_CLK					57

#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				58

#define GCC_PCIE_1_PIPE_CLK					59

#define GCC_PCIE_1_SLV_AXI_CLK					60

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				61

#define GCC_PDM2_CLK						62

#define GCC_PDM2_CLK_SRC					63

#define GCC_PDM_AHB_CLK						64

#define GCC_PDM_XO4_CLK						65

#define GCC_QMIP_CAMERA_NRT_AHB_CLK				66

#define GCC_QMIP_CAMERA_RT_AHB_CLK				67

#define GCC_QMIP_DISP_AHB_CLK					68

#define GCC_QMIP_VIDEO_CVP_AHB_CLK				69

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				70

#define GCC_QUPV3_WRAP0_CORE_2X_CLK				71

#define GCC_QUPV3_WRAP0_CORE_CLK				72

#define GCC_QUPV3_WRAP0_S0_CLK					73

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				74

#define GCC_QUPV3_WRAP0_S1_CLK					75

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				76

#define GCC_QUPV3_WRAP0_S2_CLK					77

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				78

#define GCC_QUPV3_WRAP0_S3_CLK					79

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				80

#define GCC_QUPV3_WRAP0_S4_CLK					81

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				82

#define GCC_QUPV3_WRAP0_S5_CLK					83

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				84

#define GCC_QUPV3_WRAP0_S6_CLK					85

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				86

#define GCC_QUPV3_WRAP0_S7_CLK					87

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				88

#define GCC_QUPV3_WRAP1_CORE_2X_CLK				89

#define GCC_QUPV3_WRAP1_CORE_CLK				90

#define GCC_QUPV3_WRAP1_S0_CLK					91

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				92

#define GCC_QUPV3_WRAP1_S1_CLK					93

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				94

#define GCC_QUPV3_WRAP1_S2_CLK					95

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				96

#define GCC_QUPV3_WRAP1_S3_CLK					97

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				98

#define GCC_QUPV3_WRAP1_S4_CLK					99

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				100

#define GCC_QUPV3_WRAP1_S5_CLK					101

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				102

#define GCC_QUPV3_WRAP2_CORE_2X_CLK				103

#define GCC_QUPV3_WRAP2_CORE_CLK				104

#define GCC_QUPV3_WRAP2_S0_CLK					105

#define GCC_QUPV3_WRAP2_S0_CLK_SRC				106

#define GCC_QUPV3_WRAP2_S1_CLK					107

#define GCC_QUPV3_WRAP2_S1_CLK_SRC				108

#define GCC_QUPV3_WRAP2_S2_CLK					109

#define GCC_QUPV3_WRAP2_S2_CLK_SRC				110

#define GCC_QUPV3_WRAP2_S3_CLK					111

#define GCC_QUPV3_WRAP2_S3_CLK_SRC				112

#define GCC_QUPV3_WRAP2_S4_CLK					113

#define GCC_QUPV3_WRAP2_S4_CLK_SRC				114

#define GCC_QUPV3_WRAP2_S5_CLK					115

#define GCC_QUPV3_WRAP2_S5_CLK_SRC				116

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				117

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				118

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				119

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				120

#define GCC_QUPV3_WRAP_2_M_AHB_CLK				121

#define GCC_QUPV3_WRAP_2_S_AHB_CLK				122

#define GCC_SDCC2_AHB_CLK					123

#define GCC_SDCC2_APPS_CLK					124

#define GCC_SDCC2_APPS_CLK_SRC					125

#define GCC_SDCC4_AHB_CLK					126

#define GCC_SDCC4_APPS_CLK					127

#define GCC_SDCC4_APPS_CLK_SRC					128

#define GCC_SYS_NOC_CPUSS_AHB_CLK				129

#define GCC_UFS_1_CLKREF_EN					130

#define GCC_UFS_CARD_AHB_CLK					131

#define GCC_UFS_CARD_AXI_CLK					132

#define GCC_UFS_CARD_AXI_CLK_SRC				133

#define GCC_UFS_CARD_AXI_HW_CTL_CLK				134

#define GCC_UFS_CARD_ICE_CORE_CLK				135

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				136

#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			137

#define GCC_UFS_CARD_PHY_AUX_CLK				138

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				139

#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				140

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				141

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				142

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				143

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				144

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			145

#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			146

#define GCC_UFS_PHY_AHB_CLK					147

#define GCC_UFS_PHY_AXI_CLK					148

#define GCC_UFS_PHY_AXI_CLK_SRC					149

#define GCC_UFS_PHY_AXI_HW_CTL_CLK				150

#define GCC_UFS_PHY_ICE_CORE_CLK				151

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				152

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				153

#define GCC_UFS_PHY_PHY_AUX_CLK					154

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				155

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				156

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				157

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				158

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				159

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				160

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				161

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			162

#define GCC_USB30_PRIM_MASTER_CLK				163

#define GCC_USB30_PRIM_MASTER_CLK_SRC				164

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				165

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			166

#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		167

#define GCC_USB30_PRIM_SLEEP_CLK				168

#define GCC_USB30_SEC_MASTER_CLK				169

#define GCC_USB30_SEC_MASTER_CLK_SRC				170

#define GCC_USB30_SEC_MOCK_UTMI_CLK				171

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				172

#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC			173

#define GCC_USB30_SEC_SLEEP_CLK					174

#define GCC_USB3_PRIM_PHY_AUX_CLK				175

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				176

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				177

#define GCC_USB3_PRIM_PHY_PIPE_CLK				178

#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				179

#define GCC_USB3_SEC_CLKREF_EN					180

#define GCC_USB3_SEC_PHY_AUX_CLK				181

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				182

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				183

#define GCC_USB3_SEC_PHY_PIPE_CLK				184

#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC				185

#define GCC_VIDEO_AHB_CLK					186

#define GCC_VIDEO_AXI0_CLK					187

#define GCC_VIDEO_AXI1_CLK					188

#define GCC_VIDEO_XO_CLK					189



/* GCC resets */

#define GCC_CAMERA_BCR						0