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Unverified Commit ee0b27a3 authored by Andre Przywara's avatar Andre Przywara Committed by Maxime Ripard
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clk: sunxi: A31: Fix wrong AHB gate number 



According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.

Fix the gate bit definitions in the clock driver.

Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent 5c59801f

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

+2 −2
Original line number Diff line number Diff line
@@ -264,9 +264,9 @@ static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1", 
static SUNXI_CCU_GATE(ahb1_mmc2_clk,	"ahb1-mmc2",	"ahb1",

		      0x060, BIT(10), 0);

static SUNXI_CCU_GATE(ahb1_mmc3_clk,	"ahb1-mmc3",	"ahb1",

		      0x060, BIT(12), 0);

		      0x060, BIT(11), 0);

static SUNXI_CCU_GATE(ahb1_nand1_clk,	"ahb1-nand1",	"ahb1",

		      0x060, BIT(13), 0);

		      0x060, BIT(12), 0);

static SUNXI_CCU_GATE(ahb1_nand0_clk,	"ahb1-nand0",	"ahb1",

		      0x060, BIT(13), 0);

static SUNXI_CCU_GATE(ahb1_sdram_clk,	"ahb1-sdram",	"ahb1",