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Commit eddae0d7 authored by Nilaan Gunabalachandran's avatar Nilaan Gunabalachandran Committed by Gerrit - the friendly Code Review server
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disp: msm: increase delay times while waiting to turn off rscc clocks 



RSC is timing out while checking for power control register,
increasing wait times only after a poms, removes this issue.

Change-Id: I4a324eb3c87e7dfb84d9a8b0a11597327d206a74
Signed-off-by: default avatarNilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent 1f331b53

msm/sde_rsc.c

+5 −0
Original line number Diff line number Diff line
@@ -554,6 +554,8 @@ static int sde_rsc_switch_to_cmd(struct sde_rsc_priv *rsc, 
	/* indicate wait for vsync for vid to cmd state switch & cfg update */

	if (!rc && (rsc->current_state == SDE_RSC_VID_STATE ||

			rsc->current_state == SDE_RSC_CMD_STATE)) {

		rsc->post_poms = true;



		/* clear VSYNC timestamp for indication when update completes */

		if (rsc->hw_ops.hw_vsync)

			rsc->hw_ops.hw_vsync(rsc, VSYNC_ENABLE, NULL, 0, 0);
@@ -707,6 +709,8 @@ static int sde_rsc_switch_to_vid(struct sde_rsc_priv *rsc, 
	/* indicate wait for vsync for vid to cmd state switch & cfg update */

	if (!rc && (rsc->current_state == SDE_RSC_VID_STATE ||

			rsc->current_state == SDE_RSC_CMD_STATE)) {

		rsc->post_poms = true;



		/* clear VSYNC timestamp for indication when update completes */

		if (rsc->hw_ops.hw_vsync)

			rsc->hw_ops.hw_vsync(rsc, VSYNC_ENABLE, NULL, 0, 0);
@@ -774,6 +778,7 @@ static int sde_rsc_switch_to_idle(struct sde_rsc_priv *rsc, 
			rc = CLK_MODE_SWITCH_SUCCESS;

	} else if (rsc->hw_ops.state_update) {

		rc = rsc->hw_ops.state_update(rsc, SDE_RSC_IDLE_STATE);

		rsc->post_poms = false;

		if (!rc) {

			rpmh_mode_solver_set(rsc->rpmh_dev, true);

			sde_rsc_set_data_bus_mode(&rsc->phandle,

msm/sde_rsc_hw_v3.c

+7 −1
Original line number Diff line number Diff line
@@ -278,7 +278,7 @@ static int sde_rsc_mode2_entry_trigger(struct sde_rsc_priv *rsc) 
			rc = 0;

			break;

		}

		usleep_range(10, 100);

		usleep_range(50, 100);

	}



	return rc;
@@ -343,6 +343,12 @@ static int sde_rsc_mode2_entry_v3(struct sde_rsc_priv *rsc) 
	dss_reg_w(&rsc->drv_io, SDE_RSC_SOLVER_SOLVER_MODES_ENABLED_DRV0,

						0x7, rsc->debug_mode);



	/**

	 * increase delay time to wait before mode2 entry,

	 * longer time required subsequent to panel mode change

	 */

	if (rsc->post_poms)

		usleep_range(750, 1000);

	for (i = 0; i <= MAX_MODE2_ENTRY_TRY; i++) {

		rc = sde_rsc_mode2_entry_trigger(rsc);

		if (!rc)

msm/sde_rsc_priv.h

+3 −0
Original line number Diff line number Diff line
@@ -193,6 +193,7 @@ struct sde_rsc_bw_config { 
 * resource_refcount:	Track rsc resource refcount

 * profiling_supp:	Indicates if HW has support for profiling counters

 * profiling_en:	Flag for rsc lpm profiling counters, true=enabled

 * post_poms:		bool if a panel mode change occurred

 */

struct sde_rsc_priv {

	u32 version;
@@ -236,6 +237,8 @@ struct sde_rsc_priv { 
	atomic_t resource_refcount;

	bool profiling_supp;

	bool profiling_en;



	bool post_poms;

};



/**