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Commit edd91748 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add limit rate on G4 for Lahaina rumi"

parents 06692b39 2ffdfeb8

bindings/ufs/ufs-qcom.txt

+2 −1
Original line number Diff line number Diff line
@@ -34,7 +34,8 @@ Optional properties: 
- vddp-ref-clk-supply   : phandle to UFS device ref_clk pad power supply

- vddp-ref-clk-max-microamp : specifies max. load that can be drawn from this supply

- resets : specifies the PHY reset in the UFS controller



- limit-rate : specifies if the rate has to be limited to A or B.

	       1 = rate B, 0 = rate A.

Example:



	ufsphy1: ufsphy@fc597000 {

qcom/lahaina-rumi.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
&ufshc_mem {

	limit-tx-hs-gear = <1>;

	limit-rx-hs-gear = <1>;

	limit-rate = <1>;



	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;

	vdd-hba-fixed-regulator;

qcom/lahaina.dtsi

+59 −1
Original line number Diff line number Diff line
@@ -1141,7 +1141,6 @@ 
		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";

		#reset-cells = <1>;



		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */
@@ -1175,6 +1174,65 @@ 
			<0 0>,

			<0 0>,

			<0 0>;

		interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,

		      <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;

		interconnect-names = "ufs-ddr", "cpu-ufs";



		qcom,ufs-bus-bw,name = "ufshc_mem";

		qcom,ufs-bus-bw,num-cases = <26>;

		qcom,ufs-bus-bw,num-paths = <2>;

		qcom,ufs-bus-bw,vectors-KBps =

		/*

		 * During HS G3 UFS runs at nominal voltage corner, vote

		 * higher bandwidth to push other buses in the data path

		 * to run at nominal to achieve max throughput.

		 * 4GBps pushes BIMC to run at nominal.

		 * 200MBps pushes CNOC to run at nominal.

		 * Vote for half of this bandwidth for HS G3 1-lane.

		 * For max bandwidth, vote high enough to push the buses

		 * to run in turbo voltage corner.

		 */

		<0 0>, <0 0>,          /* No vote */

		<922 0>, <1000 0>,     /* PWM G1 */

		<1844 0>, <1000 0>,    /* PWM G2 */

		<3688 0>, <1000 0>,    /* PWM G3 */

		<7376 0>, <1000 0>,    /* PWM G4 */

		<1844 0>, <1000 0>,    /* PWM G1 L2 */

		<3688 0>, <1000 0>,    /* PWM G2 L2 */

		<7376 0>, <1000 0>,    /* PWM G3 L2 */

		<14752 0>, <1000 0>,   /* PWM G4 L2 */

		<127796 0>, <1000 0>,  /* HS G1 RA */

		<255591 0>, <1000 0>,  /* HS G2 RA */

		<2097152 0>, <102400 0>,  /* HS G3 RA */

		<4194304 0>, <204800 0>,  /* HS G4 RA */

		<255591 0>, <1000 0>,  /* HS G1 RA L2 */

		<511181 0>, <1000 0>,  /* HS G2 RA L2 */

		<4194304 0>, <204800 0>, /* HS G3 RA L2 */

		<8388608 0>, <409600 0>, /* HS G4 RA L2 */

		<149422 0>, <1000 0>,  /* HS G1 RB */

		<298189 0>, <1000 0>,  /* HS G2 RB */

		<2097152 0>, <102400 0>,  /* HS G3 RB */

		<4194304 0>, <204800 0>,  /* HS G4 RB */

		<298189 0>, <1000 0>,  /* HS G1 RB L2 */

		<596378 0>, <1000 0>,  /* HS G2 RB L2 */

		/* As UFS working in HS G3 RB L2 mode, aggregated

		 * bandwidth (AB) should take care of providing

		 * optimum throughput requested. However, as tested,

		 * in order to scale up CNOC clock, instantaneous

		 * bindwidth (IB) needs to be given a proper value too.

		 */

		<4194304 0>, <204800 409600>, /* HS G3 RB L2 */

		<8388608 0>, <409600 409600>, /* HS G4 RB L2 */

		<7643136 0>, <307200 0>; /* Max. bandwidth */



		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",

		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",

		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",

		"MAX";



		reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>;