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Commit edd45e39 authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Bjorn Helgaas
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PCI: dwc: designware: Move _unroll configurations to a separate function 



No functional change. Rename dw_pcie_writel_unroll/dw_pcie_readl_unroll to
dw_pcie_writel_ob_unroll/dw_pcie_readl_ob_unroll respectively as these
functions are used to perform only outbound configurations. Also move
these _unroll configurations to a separate function.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent a509d7d9

drivers/pci/dwc/pcie-designware.c

+58 −39
Original line number Diff line number Diff line
@@ -92,14 +92,14 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, 
		dev_err(pci->dev, "write DBI address failed\n");

}



static u32 dw_pcie_readl_unroll(struct dw_pcie *pci, u32 index, u32 reg)

static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)

{

	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);



	return dw_pcie_readl_dbi(pci, offset + reg);

}



static void dw_pcie_writel_unroll(struct dw_pcie *pci, u32 index, u32 reg,

static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,

				     u32 val)

{

	u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
@@ -107,30 +107,55 @@ static void dw_pcie_writel_unroll(struct dw_pcie *pci, u32 index, u32 reg, 
	dw_pcie_writel_dbi(pci, offset + reg, val);

}



void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,

void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, int index, int type,

				      u64 cpu_addr, u64 pci_addr, u32 size)

{

	u32 retries, val;



	if (pci->ops->cpu_addr_fixup)

		cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);



	if (pci->iatu_unroll_enabled) {

		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,

				 lower_32_bits(cpu_addr));

		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,

				 upper_32_bits(cpu_addr));

		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LIMIT,

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,

				 lower_32_bits(cpu_addr + size - 1));

		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,

				 lower_32_bits(pci_addr));

		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,

				 upper_32_bits(pci_addr));

		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,

				 type);

		dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,

	dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,

				 PCIE_ATU_ENABLE);

	} else {



	/*

	 * Make sure ATU enable takes effect before any subsequent config

	 * and I/O accesses.

	 */

	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {

		val = dw_pcie_readl_ob_unroll(pci, index,

					      PCIE_ATU_UNR_REGION_CTRL2);

		if (val & PCIE_ATU_ENABLE)

			return;



		usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);

	}

	dev_err(pci->dev, "outbound iATU is not being enabled\n");

}



void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,

			       u64 cpu_addr, u64 pci_addr, u32 size)

{

	u32 retries, val;



	if (pci->ops->cpu_addr_fixup)

		cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);



	if (pci->iatu_unroll_enabled) {

		dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,

						 pci_addr, size);

		return;

	}



	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,

			   PCIE_ATU_REGION_OUTBOUND | index);

	dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
@@ -145,25 +170,19 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, 
			   upper_32_bits(pci_addr));

	dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type);

	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);

	}



	/*

	 * Make sure ATU enable takes effect before any subsequent config

	 * and I/O accesses.

	 */

	for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {

		if (pci->iatu_unroll_enabled)

			val = dw_pcie_readl_unroll(pci, index,

						   PCIE_ATU_UNR_REGION_CTRL2);

		else

		val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);



		if (val == PCIE_ATU_ENABLE)

			return;



		usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);

	}

	dev_err(pci->dev, "iATU is not being enabled\n");

	dev_err(pci->dev, "outbound iATU is not being enabled\n");

}



int dw_pcie_wait_for_link(struct dw_pcie *pci)