Loading drivers/net/wireless/cnss2/power.c +8 −2 Original line number Diff line number Diff line Loading @@ -60,7 +60,7 @@ static struct cnss_clk_cfg cnss_clk_list[] = { #define WLAN_VREGS_PROP "wlan_vregs" #define BOOTSTRAP_DELAY 1000 #define WLAN_ENABLE_DELAY 1000 #define WLAN_ENABLE_DELAY 10000 #define TCS_CMD_DATA_ADDR_OFFSET 0x4 #define TCS_OFFSET 0xC8 Loading Loading @@ -877,7 +877,13 @@ static int cnss_select_pinctrl_state(struct cnss_plat_data *plat_priv, ret); goto out; } udelay(WLAN_ENABLE_DELAY); /* As spec shown, it needs at least 4ms delay * between wlan_en become active and pcie reset * de-assert for qca6390. And it needs at least * 10ms for qca6174. So add 10ms-11ms delay here. */ usleep_range(WLAN_ENABLE_DELAY, WLAN_ENABLE_DELAY + 1000); } cnss_set_xo_clk_gpio_state(plat_priv, false); } else { Loading Loading
drivers/net/wireless/cnss2/power.c +8 −2 Original line number Diff line number Diff line Loading @@ -60,7 +60,7 @@ static struct cnss_clk_cfg cnss_clk_list[] = { #define WLAN_VREGS_PROP "wlan_vregs" #define BOOTSTRAP_DELAY 1000 #define WLAN_ENABLE_DELAY 1000 #define WLAN_ENABLE_DELAY 10000 #define TCS_CMD_DATA_ADDR_OFFSET 0x4 #define TCS_OFFSET 0xC8 Loading Loading @@ -877,7 +877,13 @@ static int cnss_select_pinctrl_state(struct cnss_plat_data *plat_priv, ret); goto out; } udelay(WLAN_ENABLE_DELAY); /* As spec shown, it needs at least 4ms delay * between wlan_en become active and pcie reset * de-assert for qca6390. And it needs at least * 10ms for qca6174. So add 10ms-11ms delay here. */ usleep_range(WLAN_ENABLE_DELAY, WLAN_ENABLE_DELAY + 1000); } cnss_set_xo_clk_gpio_state(plat_priv, false); } else { Loading