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Commit eca90f55 authored by Tushar Dave's avatar Tushar Dave Committed by Peter P Waskiewicz Jr
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e1000e: 82571 Tx Data Corruption during Tx hang recovery 



A bus trace shows that while executing e1000e_down, TCTL is cleared except
for the PSP bit.  This occurs while in the middle of fetching a TSO packet
since the Tx packet buffer is full at that point. Before the device is
reset, the e1000_watchdog_task starts to run from the middle (it was
apparently pre-empted earlier, although that is not in the trace) and sets
TCTL.EN.  At that point, 82571 transmits the corrupted packet, apparently
because TCTL.MULR was cleared in the middle of fetching a packet, which is
forbidden.

Driver should just clear TCTL.EN in e1000_reset_hw_82571 instead of
clearing the entire register, so as not to change any settings in the
middle of fetching a packet.

Signed-off-by: default avatarTushar Dave <tushar.n.dave@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarPeter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
parent b7ec70be

drivers/net/ethernet/intel/e1000e/82571.c

+4 −2
Original line number Diff line number Diff line
@@ -999,7 +999,7 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 
 **/

static s32 e1000_reset_hw_82571(struct e1000_hw *hw)

{

	u32 ctrl, ctrl_ext, eecd;

	u32 ctrl, ctrl_ext, eecd, tctl;

	s32 ret_val;



	/*
@@ -1014,7 +1014,9 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw) 
	ew32(IMC, 0xffffffff);



	ew32(RCTL, 0);

	ew32(TCTL, E1000_TCTL_PSP);

	tctl = er32(TCTL);

	tctl &= ~E1000_TCTL_EN;

	ew32(TCTL, tctl);

	e1e_flush();



	usleep_range(10000, 20000);