Commit ec338382 authored Jun 13, 2017 by Yazen Ghannam Committed by Ingo Molnar Jun 14, 2017

x86/mce: Don't disable MCA banks when offlining a CPU on AMD



AMD systems have non-core, shared MCA banks within a die. These banks
are controlled by a master CPU per die. If this CPU is offlined then all
the shared banks are disabled in addition to the CPU's core banks.

Also, Fam17h systems may have SMT enabled. The MCA_CTL register is shared
between SMT thread siblings. If a CPU is offlined then all its sibling's
MCA banks are also disabled.

Extend the existing vendor check to AMD too.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
[ Fix up comment. ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20170613162835.30750-8-bp@alien8.de


Signed-off-by: Ingo Molnar <mingo@kernel.org>

parent 86d2eac5

arch/x86/kernel/cpu/mcheck/mce.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -1912,12 +1912,13 @@ static void mce_disable_error_reporting(void)
		static void vendor_disable_error_reporting(void)
		{
		/*
		* Don't clear on Intel CPUs. Some of these MSRs are socket-wide.
		* Don't clear on Intel or AMD CPUs. Some of these MSRs are socket-wide.
		* Disabling them for just a single offlined CPU is bad, since it will
		* inhibit reporting for all shared resources on the socket like the
		* last level cache (LLC), the integrated memory controller (iMC), etc.
		*/
		if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
		if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL \|\|
		boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
		return;

		mce_disable_error_reporting();