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Commit eb4f5213 authored by Shaokun Zhang's avatar Shaokun Zhang Committed by Will Deacon
Browse files

drivers/perf: hisi: Fixup one DDRC PMU register offset 



For DDRC PMU, each PMU counter is fixed-purpose. There is a mismatch
between perf list and driver definition on rw_chg event.
# perf list | grep chg
  hisi_sccl1_ddrc0/rnk_chg/                          [Kernel PMU event]
  hisi_sccl1_ddrc0/rw_chg/                           [Kernel PMU event]
But the register offset of rw_chg event is not defined in the driver,
meanwhile bnk_chg register offset is mis-defined, let's fixup it.

Fixes: 904dcf03 ("perf: hisi: Add support for HiSilicon SoC DDRC PMU driver")
Cc: stable@vger.kernel.org
Cc: John Garry <john.garry@huawei.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Reported-by: default avatarWeijian Huang <huangweijian4@hisilicon.com>
Signed-off-by: default avatarShaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 2f328fea

drivers/perf/hisilicon/hisi_uncore_ddrc_pmu.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -30,8 +30,8 @@ 
#define DDRC_FLUX_RCMD          0x38c

#define DDRC_FLUX_RCMD          0x38c

#define DDRC_PRE_CMD            0x3c0

#define DDRC_PRE_CMD            0x3c0

#define DDRC_ACT_CMD            0x3c4

#define DDRC_ACT_CMD            0x3c4

#define DDRC_BNK_CHG            0x3c8

#define DDRC_RNK_CHG            0x3cc

#define DDRC_RNK_CHG            0x3cc

#define DDRC_RW_CHG             0x3d0

#define DDRC_EVENT_CTRL         0x6C0

#define DDRC_EVENT_CTRL         0x6C0

#define DDRC_INT_MASK		0x6c8

#define DDRC_INT_MASK		0x6c8

#define DDRC_INT_STATUS		0x6cc

#define DDRC_INT_STATUS		0x6cc
@@ -51,7 +51,7 @@ 




static const u32 ddrc_reg_off[] = {

static const u32 ddrc_reg_off[] = {

	DDRC_FLUX_WR, DDRC_FLUX_RD, DDRC_FLUX_WCMD, DDRC_FLUX_RCMD,

	DDRC_FLUX_WR, DDRC_FLUX_RD, DDRC_FLUX_WCMD, DDRC_FLUX_RCMD,

	DDRC_PRE_CMD, DDRC_ACT_CMD, DDRC_BNK_CHG, DDRC_RNK_CHG

	DDRC_PRE_CMD, DDRC_ACT_CMD, DDRC_RNK_CHG, DDRC_RW_CHG

};

};





/*

/*