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Commit eaf76b21 authored by Tang Yuantian's avatar Tang Yuantian Committed by Scott Wood
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clk: qoriq: Update the clock bindings 



Main changs include:
	- Clarified the clock nodes' version number
	- Fixed a issue in example

Singed-off-by: default avatarTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent 83e267d7

Documentation/devicetree/bindings/clock/corenet-clock.txt→Documentation/devicetree/bindings/clock/qoriq-clock.txt

+9 −1
Original line number Diff line number Diff line
@@ -7,6 +7,14 @@ which can then be passed to a variety of internal logic, including 
cores and peripheral IP blocks.

Please refer to the Reference Manual for details.



All references to "1.0" and "2.0" refer to the QorIQ chassis version to

which the chip complies.



Chassis Version		Example Chips

---------------		-------------

1.0			p4080, p5020, p5040

2.0			t4240, b4860, t1040



1. Clock Block Binding



Required properties:
@@ -85,7 +93,7 @@ Example for clock block and clock provider: 
			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-1.0";

			clock-output-names = "sysclk";

		}

		};



		pll0: pll0@800 {

			#clock-cells = <1>;