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Commit eaf522f6 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Make i915_check_and_clear_faults take intel_gt 



Continuing the conversion and elimination of implicit dev_priv.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Suggested-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190621070811.7006-6-tvrtko.ursulin@linux.intel.com
parent 99f2eb96

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+3 −1
Original line number Diff line number Diff line
@@ -28,6 +28,8 @@ 


#include "i915_drv.h"



#include "gt/intel_gt.h"



#include "intel_engine.h"

#include "intel_engine_pm.h"

#include "intel_context.h"
@@ -453,7 +455,7 @@ int intel_engines_init_mmio(struct drm_i915_private *i915) 


	RUNTIME_INFO(i915)->num_engines = hweight32(mask);



	i915_check_and_clear_faults(i915);

	intel_gt_check_and_clear_faults(&i915->gt);



	intel_setup_engine_capabilities(i915);

drivers/gpu/drm/i915/gt/intel_gt.c

+130 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 


#include "intel_gt.h"

#include "intel_gt_pm.h"

#include "intel_uncore.h"



void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)

{
@@ -20,3 +21,132 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) 


	intel_gt_pm_init_early(gt);

}



static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)

{

	intel_uncore_rmw(uncore, reg, 0, set);

}



static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)

{

	intel_uncore_rmw(uncore, reg, clr, 0);

}



static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)

{

	intel_uncore_rmw(uncore, reg, 0, 0);

}



static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)

{

	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);

	GEN6_RING_FAULT_REG_POSTING_READ(engine);

}



void

intel_gt_clear_error_registers(struct intel_gt *gt,

			       intel_engine_mask_t engine_mask)

{

	struct drm_i915_private *i915 = gt->i915;

	struct intel_uncore *uncore = gt->uncore;

	u32 eir;



	if (!IS_GEN(i915, 2))

		clear_register(uncore, PGTBL_ER);



	if (INTEL_GEN(i915) < 4)

		clear_register(uncore, IPEIR(RENDER_RING_BASE));

	else

		clear_register(uncore, IPEIR_I965);



	clear_register(uncore, EIR);

	eir = intel_uncore_read(uncore, EIR);

	if (eir) {

		/*

		 * some errors might have become stuck,

		 * mask them.

		 */

		DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);

		rmw_set(uncore, EMR, eir);

		intel_uncore_write(uncore, GEN2_IIR,

				   I915_MASTER_ERROR_INTERRUPT);

	}



	if (INTEL_GEN(i915) >= 8) {

		rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);

		intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);

	} else if (INTEL_GEN(i915) >= 6) {

		struct intel_engine_cs *engine;

		enum intel_engine_id id;



		for_each_engine_masked(engine, i915, engine_mask, id)

			gen8_clear_engine_error_register(engine);

	}

}



static void gen6_check_faults(struct intel_gt *gt)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	u32 fault;



	for_each_engine(engine, gt->i915, id) {

		fault = GEN6_RING_FAULT_REG_READ(engine);

		if (fault & RING_FAULT_VALID) {

			DRM_DEBUG_DRIVER("Unexpected fault\n"

					 "\tAddr: 0x%08lx\n"

					 "\tAddress space: %s\n"

					 "\tSource ID: %d\n"

					 "\tType: %d\n",

					 fault & PAGE_MASK,

					 fault & RING_FAULT_GTTSEL_MASK ?

					 "GGTT" : "PPGTT",

					 RING_FAULT_SRCID(fault),

					 RING_FAULT_FAULT_TYPE(fault));

		}

	}

}



static void gen8_check_faults(struct intel_gt *gt)

{

	struct intel_uncore *uncore = gt->uncore;

	u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);



	if (fault & RING_FAULT_VALID) {

		u32 fault_data0, fault_data1;

		u64 fault_addr;



		fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0);

		fault_data1 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA1);

		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |

			     ((u64)fault_data0 << 12);



		DRM_DEBUG_DRIVER("Unexpected fault\n"

				 "\tAddr: 0x%08x_%08x\n"

				 "\tAddress space: %s\n"

				 "\tEngine ID: %d\n"

				 "\tSource ID: %d\n"

				 "\tType: %d\n",

				 upper_32_bits(fault_addr),

				 lower_32_bits(fault_addr),

				 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",

				 GEN8_RING_FAULT_ENGINE_ID(fault),

				 RING_FAULT_SRCID(fault),

				 RING_FAULT_FAULT_TYPE(fault));

	}

}



void intel_gt_check_and_clear_faults(struct intel_gt *gt)

{

	struct drm_i915_private *i915 = gt->i915;



	/* From GEN8 onwards we only have one 'All Engine Fault Register' */

	if (INTEL_GEN(i915) >= 8)

		gen8_check_faults(gt);

	else if (INTEL_GEN(i915) >= 6)

		gen6_check_faults(gt);

	else

		return;



	intel_gt_clear_error_registers(gt, ALL_ENGINES);

}

drivers/gpu/drm/i915/gt/intel_gt.h

+5 −0
Original line number Diff line number Diff line
@@ -6,10 +6,15 @@ 
#ifndef __INTEL_GT__

#define __INTEL_GT__



#include "intel_engine_types.h"

#include "intel_gt_types.h"



struct drm_i915_private;



void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);



void intel_gt_check_and_clear_faults(struct intel_gt *gt);

void intel_gt_clear_error_registers(struct intel_gt *gt,

				    intel_engine_mask_t engine_mask);



#endif /* __INTEL_GT_H__ */

drivers/gpu/drm/i915/gt/intel_reset.c

+2 −124
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include "i915_gpu_error.h"

#include "i915_irq.h"

#include "intel_engine_pm.h"

#include "intel_gt.h"

#include "intel_gt_pm.h"

#include "intel_reset.h"
@@ -25,16 +26,6 @@ 
/* XXX How to handle concurrent GGTT updates using tiling registers? */

#define RESET_UNDER_STOP_MACHINE 0



static void rmw_set(struct intel_uncore *uncore, i915_reg_t reg, u32 set)

{

	intel_uncore_rmw(uncore, reg, 0, set);

}



static void rmw_clear(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)

{

	intel_uncore_rmw(uncore, reg, clr, 0);

}



static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)

{

	intel_uncore_rmw_fw(uncore, reg, 0, set);
@@ -1157,119 +1148,6 @@ static void i915_reset_device(struct drm_i915_private *i915, 
		kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);

}



static void clear_register(struct intel_uncore *uncore, i915_reg_t reg)

{

	intel_uncore_rmw(uncore, reg, 0, 0);

}



static void gen8_clear_engine_error_register(struct intel_engine_cs *engine)

{

	GEN6_RING_FAULT_REG_RMW(engine, RING_FAULT_VALID, 0);

	GEN6_RING_FAULT_REG_POSTING_READ(engine);

}



static void clear_error_registers(struct drm_i915_private *i915,

				  intel_engine_mask_t engine_mask)

{

	struct intel_uncore *uncore = &i915->uncore;

	u32 eir;



	if (!IS_GEN(i915, 2))

		clear_register(uncore, PGTBL_ER);



	if (INTEL_GEN(i915) < 4)

		clear_register(uncore, IPEIR(RENDER_RING_BASE));

	else

		clear_register(uncore, IPEIR_I965);



	clear_register(uncore, EIR);

	eir = intel_uncore_read(uncore, EIR);

	if (eir) {

		/*

		 * some errors might have become stuck,

		 * mask them.

		 */

		DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);

		rmw_set(uncore, EMR, eir);

		intel_uncore_write(uncore, GEN2_IIR,

				   I915_MASTER_ERROR_INTERRUPT);

	}



	if (INTEL_GEN(i915) >= 8) {

		rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);

		intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);

	} else if (INTEL_GEN(i915) >= 6) {

		struct intel_engine_cs *engine;

		enum intel_engine_id id;



		for_each_engine_masked(engine, i915, engine_mask, id)

			gen8_clear_engine_error_register(engine);

	}

}



static void gen6_check_faults(struct drm_i915_private *dev_priv)

{

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	u32 fault;



	for_each_engine(engine, dev_priv, id) {

		fault = GEN6_RING_FAULT_REG_READ(engine);

		if (fault & RING_FAULT_VALID) {

			DRM_DEBUG_DRIVER("Unexpected fault\n"

					 "\tAddr: 0x%08lx\n"

					 "\tAddress space: %s\n"

					 "\tSource ID: %d\n"

					 "\tType: %d\n",

					 fault & PAGE_MASK,

					 fault & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",

					 RING_FAULT_SRCID(fault),

					 RING_FAULT_FAULT_TYPE(fault));

		}

	}

}



static void gen8_check_faults(struct drm_i915_private *dev_priv)

{

	u32 fault = I915_READ(GEN8_RING_FAULT_REG);



	if (fault & RING_FAULT_VALID) {

		u32 fault_data0, fault_data1;

		u64 fault_addr;



		fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);

		fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);

		fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |

			     ((u64)fault_data0 << 12);



		DRM_DEBUG_DRIVER("Unexpected fault\n"

				 "\tAddr: 0x%08x_%08x\n"

				 "\tAddress space: %s\n"

				 "\tEngine ID: %d\n"

				 "\tSource ID: %d\n"

				 "\tType: %d\n",

				 upper_32_bits(fault_addr),

				 lower_32_bits(fault_addr),

				 fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",

				 GEN8_RING_FAULT_ENGINE_ID(fault),

				 RING_FAULT_SRCID(fault),

				 RING_FAULT_FAULT_TYPE(fault));

	}

}



void i915_check_and_clear_faults(struct drm_i915_private *i915)

{

	/* From GEN8 onwards we only have one 'All Engine Fault Register' */

	if (INTEL_GEN(i915) >= 8)

		gen8_check_faults(i915);

	else if (INTEL_GEN(i915) >= 6)

		gen6_check_faults(i915);

	else

		return;



	clear_error_registers(i915, ALL_ENGINES);

}



/**

 * i915_handle_error - handle a gpu error

 * @i915: i915 device private
@@ -1318,7 +1196,7 @@ void i915_handle_error(struct drm_i915_private *i915, 


	if (flags & I915_ERROR_CAPTURE) {

		i915_capture_error_state(i915, engine_mask, msg);

		clear_error_registers(i915, engine_mask);

		intel_gt_clear_error_registers(&i915->gt, engine_mask);

	}



	/*

drivers/gpu/drm/i915/gt/intel_reset.h

+0 −2
Original line number Diff line number Diff line
@@ -25,8 +25,6 @@ void i915_handle_error(struct drm_i915_private *i915, 
		       const char *fmt, ...);

#define I915_ERROR_CAPTURE BIT(0)



void i915_check_and_clear_faults(struct drm_i915_private *i915);



void i915_reset(struct drm_i915_private *i915,

		intel_engine_mask_t stalled_mask,

		const char *reason);