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Commit eabbb7f8 authored by Elson Roy Serrao's avatar Elson Roy Serrao
Browse files

usb: dwc3: core: Select UTMI clock before core_soft_reset 



In HS Only mode of dwc3 controller version 1.9A, UTMI clock needs
to be selected before core soft reset as per the HPG sequence.
Or else the core soft reset fails, leading to enumeration
failure. Hence select UTMI clock before performing
SOFT_RESET operation.

Change-Id: I12d4a992872eecbfc38825282559cd4d592c3896
Signed-off-by: default avatarElson Roy Serrao <eserrao@codeaurora.org>
parent 47f285b8

drivers/usb/dwc3/core.c

+0 −2
Original line number Diff line number Diff line
@@ -1120,8 +1120,6 @@ int dwc3_core_init(struct dwc3 *dwc) 
		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);

	}



	dwc3_notify_event(dwc, DWC3_CONTROLLER_POST_RESET_EVENT, 0);



	return 0;



err3:

drivers/usb/dwc3/core.h

+0 −1
Original line number Diff line number Diff line
@@ -1695,7 +1695,6 @@ static inline void dwc3_ulpi_exit(struct dwc3 *dwc) 
enum dwc3_notify_event {

	DWC3_CONTROLLER_ERROR_EVENT,

	DWC3_CONTROLLER_RESET_EVENT,

	DWC3_CONTROLLER_POST_RESET_EVENT,

	DWC3_CORE_PM_SUSPEND_EVENT,

	DWC3_CORE_PM_RESUME_EVENT,

	DWC3_CONTROLLER_CONNDONE_EVENT,

drivers/usb/dwc3/dwc3-msm.c

+29 −34
Original line number Diff line number Diff line
@@ -2339,40 +2339,6 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, 
		if (dwc->retries_on_error < MAX_ERROR_RECOVERY_TRIES)

			schedule_work(&mdwc->restart_usb_work);

		break;

	case DWC3_CONTROLLER_POST_RESET_EVENT:

		dev_dbg(mdwc->dev,

				"DWC3_CONTROLLER_POST_RESET_EVENT received\n");



		/*

		 * Below sequence is used when controller is working without

		 * having ssphy and only USB high/full speed is supported.

		 */

		if (dwc->maximum_speed == USB_SPEED_HIGH ||

					dwc->maximum_speed == USB_SPEED_FULL) {

			dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG,

				dwc3_msm_read_reg(mdwc->base,

				QSCRATCH_GENERAL_CFG)

				| PIPE_UTMI_CLK_DIS);



			usleep_range(2, 5);





			dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG,

				dwc3_msm_read_reg(mdwc->base,

				QSCRATCH_GENERAL_CFG)

				| PIPE_UTMI_CLK_SEL

				| PIPE3_PHYSTATUS_SW);



			usleep_range(2, 5);



			dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG,

				dwc3_msm_read_reg(mdwc->base,

				QSCRATCH_GENERAL_CFG)

				& ~PIPE_UTMI_CLK_DIS);

		}



		dwc->tx_fifo_size = mdwc->tx_fifo_size;

		break;

	case DWC3_CONTROLLER_CONNDONE_EVENT:

		dev_dbg(mdwc->dev, "DWC3_CONTROLLER_CONNDONE_EVENT received\n");

		/*
@@ -2588,6 +2554,35 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc) 
		clk_disable_unprepare(mdwc->cfg_ahb_clk);

	}



	/*

	 * Below sequence is used when controller is working without

	 * having ssphy and only USB high/full speed is supported.

	 */

	if (dwc->maximum_speed == USB_SPEED_HIGH ||

				dwc->maximum_speed == USB_SPEED_FULL) {

		dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG,

			dwc3_msm_read_reg(mdwc->base,

			QSCRATCH_GENERAL_CFG)

			| PIPE_UTMI_CLK_DIS);



		usleep_range(2, 5);





		dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG,

			dwc3_msm_read_reg(mdwc->base,

			QSCRATCH_GENERAL_CFG)

			| PIPE_UTMI_CLK_SEL

			| PIPE3_PHYSTATUS_SW);



		usleep_range(2, 5);



		dwc3_msm_write_reg(mdwc->base, QSCRATCH_GENERAL_CFG,

			dwc3_msm_read_reg(mdwc->base,

			QSCRATCH_GENERAL_CFG)

			& ~PIPE_UTMI_CLK_DIS);

	}



	dwc->tx_fifo_size = mdwc->tx_fifo_size;

	ret = dwc3_core_init(dwc);

	if (ret)

		dev_err(mdwc->dev, "%s: dwc3_core init failed (%d)\n",