Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ea2cec24 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2019-04-05' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Pretty quiet week, just some amdgpu and i915 fixes.

  i915:
   - deadlock fix
   - gvt fixes

  amdgpu:
   - PCIE dpm feature fix
   - Powerplay fixes"

* tag 'drm-fixes-2019-04-05' of git://anongit.freedesktop.org/drm/drm:
  drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplug
  drm/i915/gvt: Correct the calculation of plane size
  drm/amdgpu: remove unnecessary rlc reset function on gfx9
  drm/i915: Always backoff after a drm_modeset_lock() deadlock
  drm/i915/gvt: do not let pin count of shadow mm go negative
  drm/i915/gvt: do not deliver a workload if its creation fails
  drm/amd/display: VBIOS can't be light up HDMI when restart system
  drm/amd/powerplay: fix possible hang with 3+ 4K monitors
  drm/amd/powerplay: correct data type to avoid overflow
  drm/amd/powerplay: add ECC feature bit
  drm/amd/amdgpu: fix PCIe dpm feature issue (v3)
parents 0548740e 23b5f422

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+5 −0
Original line number Diff line number Diff line
@@ -3625,6 +3625,7 @@ static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev, 
	struct pci_dev *pdev = adev->pdev;

	enum pci_bus_speed cur_speed;

	enum pcie_link_width cur_width;

	u32 ret = 1;



	*speed = PCI_SPEED_UNKNOWN;

	*width = PCIE_LNK_WIDTH_UNKNOWN;
@@ -3632,6 +3633,10 @@ static void amdgpu_device_get_min_pci_speed_width(struct amdgpu_device *adev, 
	while (pdev) {

		cur_speed = pcie_get_speed_cap(pdev);

		cur_width = pcie_get_width_cap(pdev);

		ret = pcie_bandwidth_available(adev->pdev, NULL,

						       NULL, &cur_width);

		if (!ret)

			cur_width = PCIE_LNK_WIDTH_RESRV;



		if (cur_speed != PCI_SPEED_UNKNOWN) {

			if (*speed == PCI_SPEED_UNKNOWN)

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+0 −2
Original line number Diff line number Diff line
@@ -2405,8 +2405,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 
	/* disable CG */

	WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);



	adev->gfx.rlc.funcs->reset(adev);



	gfx_v9_0_init_pg(adev);



	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+6 −0
Original line number Diff line number Diff line
@@ -2660,12 +2660,18 @@ void core_link_enable_stream( 
void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)

{

	struct dc  *core_dc = pipe_ctx->stream->ctx->dc;

	struct dc_stream_state *stream = pipe_ctx->stream;



	core_dc->hwss.blank_stream(pipe_ctx);



	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

		deallocate_mst_payload(pipe_ctx);



	if (dc_is_hdmi_signal(pipe_ctx->stream->signal))

		dal_ddc_service_write_scdc_data(

			stream->link->ddc, 0,

			stream->timing.flags.LTE_340MCSC_SCRAMBLE);



	core_dc->hwss.disable_stream(pipe_ctx, option);



	disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

+18 −2
Original line number Diff line number Diff line
@@ -91,6 +91,12 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr) 
	 *   MP0CLK DS

	 */

	data->registry_data.disallowed_features = 0xE0041C00;

	/* ECC feature should be disabled on old SMUs */

	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);

	hwmgr->smu_version = smum_get_argument(hwmgr);

	if (hwmgr->smu_version < 0x282100)

		data->registry_data.disallowed_features |= FEATURE_ECC_MASK;



	data->registry_data.od_state_in_dc_support = 0;

	data->registry_data.thermal_support = 1;

	data->registry_data.skip_baco_hardware = 0;
@@ -357,6 +363,7 @@ static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr) 
	data->smu_features[GNLD_DS_MP1CLK].smu_feature_id = FEATURE_DS_MP1CLK_BIT;

	data->smu_features[GNLD_DS_MP0CLK].smu_feature_id = FEATURE_DS_MP0CLK_BIT;

	data->smu_features[GNLD_XGMI].smu_feature_id = FEATURE_XGMI_BIT;

	data->smu_features[GNLD_ECC].smu_feature_id = FEATURE_ECC_BIT;



	for (i = 0; i < GNLD_FEATURES_MAX; i++) {

		data->smu_features[i].smu_feature_bitmap =
@@ -3020,7 +3027,8 @@ static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) 
				"FCLK_DS",

				"MP1CLK_DS",

				"MP0CLK_DS",

				"XGMI"};

				"XGMI",

				"ECC"};

	static const char *output_title[] = {

				"FEATURES",

				"BITMASK",
@@ -3462,6 +3470,7 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) 
	struct vega20_single_dpm_table *dpm_table;

	bool vblank_too_short = false;

	bool disable_mclk_switching;

	bool disable_fclk_switching;

	uint32_t i, latency;



	disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
@@ -3537,13 +3546,20 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) 
	if (hwmgr->display_config->nb_pstate_switch_disable)

		dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;



	if ((disable_mclk_switching &&

	    (dpm_table->dpm_state.hard_min_level == dpm_table->dpm_levels[dpm_table->count - 1].value)) ||

	     hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)

		disable_fclk_switching = true;

	else

		disable_fclk_switching = false;



	/* fclk */

	dpm_table = &(data->dpm_table.fclk_table);

	dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;

	dpm_table->dpm_state.soft_max_level = VG20_CLOCK_MAX_DEFAULT;

	dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;

	dpm_table->dpm_state.hard_max_level = VG20_CLOCK_MAX_DEFAULT;

	if (hwmgr->display_config->nb_pstate_switch_disable)

	if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)

		dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;



	/* vclk */

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.h

+1 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ enum { 
	GNLD_DS_MP1CLK,

	GNLD_DS_MP0CLK,

	GNLD_XGMI,

	GNLD_ECC,



	GNLD_FEATURES_MAX

};