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Commit e9c9eeca authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-cpufeature-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpufeature updates from Ingo Molnar:
 "The main changes in this cycle were:

   - Continued cleanups of CPU bugs mis-marked as 'missing features', by
     Borislav Petkov.

   - Detect the xsaves/xrstors feature and releated cleanup, by Fenghua
     Yu"

* 'x86-cpufeature-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, cpu: Kill cpu_has_mp
  x86, amd: Cleanup init_amd
  x86/cpufeature: Add bug flags to /proc/cpuinfo
  x86, cpufeature: Convert more "features" to bugs
  x86/xsaves: Detect xsaves/xrstors feature
  x86/cpufeature.h: Reformat x86 feature macros
parents 19d402c1 af0fa6f6

arch/x86/include/asm/apic.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -99,7 +99,7 @@ static inline void native_apic_mem_write(u32 reg, u32 v) 
{

{

	volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);

	volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);





	alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,

	alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP,

		       ASM_OUTPUT2("=r" (v), "=m" (*addr)),

		       ASM_OUTPUT2("=r" (v), "=m" (*addr)),

		       ASM_OUTPUT2("0" (v), "m" (*addr)));

		       ASM_OUTPUT2("0" (v), "m" (*addr)));

}

}

arch/x86/include/asm/cpufeature.h

+210 −199
Original line number Original line Diff line number Diff line
@@ -8,7 +8,7 @@ 
#include <asm/required-features.h>

#include <asm/required-features.h>

#endif

#endif





#define NCAPINTS	10	/* N 32-bit words worth of info */

#define NCAPINTS	11	/* N 32-bit words worth of info */

#define NBUGINTS	1	/* N 32-bit bug flags */

#define NBUGINTS	1	/* N 32-bit bug flags */





/*

/*
@@ -81,7 +81,7 @@ 
#define X86_FEATURE_P4		( 3*32+ 7) /* "" P4 */

#define X86_FEATURE_P4		( 3*32+ 7) /* "" P4 */

#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */

#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */

#define X86_FEATURE_UP		( 3*32+ 9) /* smp kernel running on up */

#define X86_FEATURE_UP		( 3*32+ 9) /* smp kernel running on up */

#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */

/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */

#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */

#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */

#define X86_FEATURE_PEBS	( 3*32+12) /* Precise-Event Based Sampling */

#define X86_FEATURE_PEBS	( 3*32+12) /* Precise-Event Based Sampling */

#define X86_FEATURE_BTS		( 3*32+13) /* Branch Trace Store */

#define X86_FEATURE_BTS		( 3*32+13) /* Branch Trace Store */
@@ -90,13 +90,13 @@ 
#define X86_FEATURE_REP_GOOD	( 3*32+16) /* rep microcode works well */

#define X86_FEATURE_REP_GOOD	( 3*32+16) /* rep microcode works well */

#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */

#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */

#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */

#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */

#define X86_FEATURE_11AP	(3*32+19) /* "" Bad local APIC aka 11AP */

/* free, was #define X86_FEATURE_11AP	( 3*32+19) * "" Bad local APIC aka 11AP */

#define X86_FEATURE_NOPL	( 3*32+20) /* The NOPL (0F 1F) instructions */

#define X86_FEATURE_NOPL	( 3*32+20) /* The NOPL (0F 1F) instructions */

#define X86_FEATURE_ALWAYS	( 3*32+21) /* "" Always-present feature */

#define X86_FEATURE_ALWAYS	( 3*32+21) /* "" Always-present feature */

#define X86_FEATURE_XTOPOLOGY	( 3*32+22) /* cpu topology enum extensions */

#define X86_FEATURE_XTOPOLOGY	( 3*32+22) /* cpu topology enum extensions */

#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */

#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */

#define X86_FEATURE_NONSTOP_TSC	( 3*32+24) /* TSC does not stop in C states */

#define X86_FEATURE_NONSTOP_TSC	( 3*32+24) /* TSC does not stop in C states */

#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */

/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */

#define X86_FEATURE_EXTD_APICID	( 3*32+26) /* has extended APICID (8 bits) */

#define X86_FEATURE_EXTD_APICID	( 3*32+26) /* has extended APICID (8 bits) */

#define X86_FEATURE_AMD_DCM     ( 3*32+27) /* multi-node processor */

#define X86_FEATURE_AMD_DCM     ( 3*32+27) /* multi-node processor */

#define X86_FEATURE_APERFMPERF	( 3*32+28) /* APERFMPERF */

#define X86_FEATURE_APERFMPERF	( 3*32+28) /* APERFMPERF */
@@ -180,7 +180,6 @@ 
#define X86_FEATURE_ARAT	( 7*32+ 1) /* Always Running APIC Timer */

#define X86_FEATURE_ARAT	( 7*32+ 1) /* Always Running APIC Timer */

#define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */

#define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */

#define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */

#define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */

#define X86_FEATURE_XSAVEOPT	(7*32+ 4) /* Optimized Xsave */

#define X86_FEATURE_PLN		( 7*32+ 5) /* Intel Power Limit Notification */

#define X86_FEATURE_PLN		( 7*32+ 5) /* Intel Power Limit Notification */

#define X86_FEATURE_PTS		( 7*32+ 6) /* Intel Package Thermal Status */

#define X86_FEATURE_PTS		( 7*32+ 6) /* Intel Package Thermal Status */

#define X86_FEATURE_DTHERM	( 7*32+ 7) /* Digital Thermal Sensor */

#define X86_FEATURE_DTHERM	( 7*32+ 7) /* Digital Thermal Sensor */
@@ -226,6 +225,12 @@ 
#define X86_FEATURE_AVX512ER	( 9*32+27) /* AVX-512 Exponential and Reciprocal */

#define X86_FEATURE_AVX512ER	( 9*32+27) /* AVX-512 Exponential and Reciprocal */

#define X86_FEATURE_AVX512CD	( 9*32+28) /* AVX-512 Conflict Detection */

#define X86_FEATURE_AVX512CD	( 9*32+28) /* AVX-512 Conflict Detection */





/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */

#define X86_FEATURE_XSAVEOPT	(10*32+ 0) /* XSAVEOPT */

#define X86_FEATURE_XSAVEC	(10*32+ 1) /* XSAVEC */

#define X86_FEATURE_XGETBV1	(10*32+ 2) /* XGETBV with ECX = 1 */

#define X86_FEATURE_XSAVES	(10*32+ 3) /* XSAVES/XRSTORS */



/*

/*

 * BUG word(s)

 * BUG word(s)

 */

 */
@@ -234,8 +239,11 @@ 
#define X86_BUG_F00F		X86_BUG(0) /* Intel F00F */

#define X86_BUG_F00F		X86_BUG(0) /* Intel F00F */

#define X86_BUG_FDIV		X86_BUG(1) /* FPU FDIV */

#define X86_BUG_FDIV		X86_BUG(1) /* FPU FDIV */

#define X86_BUG_COMA		X86_BUG(2) /* Cyrix 6x86 coma */

#define X86_BUG_COMA		X86_BUG(2) /* Cyrix 6x86 coma */

#define X86_BUG_AMD_TLB_MMATCH	X86_BUG(3) /* AMD Erratum 383 */

#define X86_BUG_AMD_TLB_MMATCH	X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */

#define X86_BUG_AMD_APIC_C1E	X86_BUG(4) /* AMD Erratum 400 */

#define X86_BUG_AMD_APIC_C1E	X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */

#define X86_BUG_11AP		X86_BUG(5) /* Bad local APIC aka 11AP */

#define X86_BUG_FXSAVE_LEAK	X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */

#define X86_BUG_CLFLUSH_MONITOR	X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */





#if defined(__KERNEL__) && !defined(__ASSEMBLY__)

#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
@@ -245,6 +253,12 @@ 
extern const char * const x86_cap_flags[NCAPINTS*32];

extern const char * const x86_cap_flags[NCAPINTS*32];

extern const char * const x86_power_flags[32];

extern const char * const x86_power_flags[32];





/*

 * In order to save room, we index into this array by doing

 * X86_BUG_<name> - NCAPINTS*32.

 */

extern const char * const x86_bug_flags[NBUGINTS*32];



#define test_cpu_cap(c, bit)						\

#define test_cpu_cap(c, bit)						\

	 test_bit(bit, (unsigned long *)((c)->x86_capability))

	 test_bit(bit, (unsigned long *)((c)->x86_capability))
@@ -301,7 +315,6 @@ extern const char * const x86_power_flags[32]; 
#define cpu_has_avx		boot_cpu_has(X86_FEATURE_AVX)

#define cpu_has_avx		boot_cpu_has(X86_FEATURE_AVX)

#define cpu_has_avx2		boot_cpu_has(X86_FEATURE_AVX2)

#define cpu_has_avx2		boot_cpu_has(X86_FEATURE_AVX2)

#define cpu_has_ht		boot_cpu_has(X86_FEATURE_HT)

#define cpu_has_ht		boot_cpu_has(X86_FEATURE_HT)

#define cpu_has_mp		boot_cpu_has(X86_FEATURE_MP)

#define cpu_has_nx		boot_cpu_has(X86_FEATURE_NX)

#define cpu_has_nx		boot_cpu_has(X86_FEATURE_NX)

#define cpu_has_k6_mtrr		boot_cpu_has(X86_FEATURE_K6_MTRR)

#define cpu_has_k6_mtrr		boot_cpu_has(X86_FEATURE_K6_MTRR)

#define cpu_has_cyrix_arr	boot_cpu_has(X86_FEATURE_CYRIX_ARR)

#define cpu_has_cyrix_arr	boot_cpu_has(X86_FEATURE_CYRIX_ARR)
@@ -328,6 +341,7 @@ extern const char * const x86_power_flags[32]; 
#define cpu_has_x2apic		boot_cpu_has(X86_FEATURE_X2APIC)

#define cpu_has_x2apic		boot_cpu_has(X86_FEATURE_X2APIC)

#define cpu_has_xsave		boot_cpu_has(X86_FEATURE_XSAVE)

#define cpu_has_xsave		boot_cpu_has(X86_FEATURE_XSAVE)

#define cpu_has_xsaveopt	boot_cpu_has(X86_FEATURE_XSAVEOPT)

#define cpu_has_xsaveopt	boot_cpu_has(X86_FEATURE_XSAVEOPT)

#define cpu_has_xsaves		boot_cpu_has(X86_FEATURE_XSAVES)

#define cpu_has_osxsave		boot_cpu_has(X86_FEATURE_OSXSAVE)

#define cpu_has_osxsave		boot_cpu_has(X86_FEATURE_OSXSAVE)

#define cpu_has_hypervisor	boot_cpu_has(X86_FEATURE_HYPERVISOR)

#define cpu_has_hypervisor	boot_cpu_has(X86_FEATURE_HYPERVISOR)

#define cpu_has_pclmulqdq	boot_cpu_has(X86_FEATURE_PCLMULQDQ)

#define cpu_has_pclmulqdq	boot_cpu_has(X86_FEATURE_PCLMULQDQ)
@@ -347,9 +361,6 @@ extern const char * const x86_power_flags[32]; 
#undef  cpu_has_pae

#undef  cpu_has_pae

#define cpu_has_pae		___BUG___

#define cpu_has_pae		___BUG___





#undef  cpu_has_mp

#define cpu_has_mp		1



#undef  cpu_has_k6_mtrr

#undef  cpu_has_k6_mtrr

#define cpu_has_k6_mtrr		0

#define cpu_has_k6_mtrr		0
@@ -541,9 +552,10 @@ static __always_inline __pure bool _static_cpu_has_safe(u16 bit) 




#define cpu_has_bug(c, bit)		cpu_has(c, (bit))

#define cpu_has_bug(c, bit)		cpu_has(c, (bit))

#define set_cpu_bug(c, bit)		set_cpu_cap(c, (bit))

#define set_cpu_bug(c, bit)		set_cpu_cap(c, (bit))

#define clear_cpu_bug(c, bit)	clear_cpu_cap(c, (bit));

#define clear_cpu_bug(c, bit)		clear_cpu_cap(c, (bit))





#define static_cpu_has_bug(bit)		static_cpu_has((bit))

#define static_cpu_has_bug(bit)		static_cpu_has((bit))

#define static_cpu_has_bug_safe(bit)	static_cpu_has_safe((bit))

#define boot_cpu_has_bug(bit)		cpu_has_bug(&boot_cpu_data, (bit))

#define boot_cpu_has_bug(bit)		cpu_has_bug(&boot_cpu_data, (bit))





#define MAX_CPU_FEATURES		(NCAPINTS * 32)

#define MAX_CPU_FEATURES		(NCAPINTS * 32)
@@ -554,5 +566,4 @@ static __always_inline __pure bool _static_cpu_has_safe(u16 bit) 
					boot_cpu_data.x86_model

					boot_cpu_data.x86_model





#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */

#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */



#endif /* _ASM_X86_CPUFEATURE_H */
 
#endif /* _ASM_X86_CPUFEATURE_H */

arch/x86/include/asm/fpu-internal.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -293,7 +293,7 @@ static inline int restore_fpu_checking(struct task_struct *tsk) 
	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception

	/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception

	   is pending.  Clear the x87 state here by setting it to fixed

	   is pending.  Clear the x87 state here by setting it to fixed

	   values. "m" is a random variable that should be in L1 */

	   values. "m" is a random variable that should be in L1 */

	if (unlikely(static_cpu_has_safe(X86_FEATURE_FXSAVE_LEAK))) {

	if (unlikely(static_cpu_has_bug_safe(X86_BUG_FXSAVE_LEAK))) {

		asm volatile(

		asm volatile(

			"fnclex\n\t"

			"fnclex\n\t"

			"emms\n\t"

			"emms\n\t"

arch/x86/include/asm/mwait.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -43,7 +43,7 @@ static inline void __mwait(unsigned long eax, unsigned long ecx) 
static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)

static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)

{

{

	if (!current_set_polling_and_test()) {

	if (!current_set_polling_and_test()) {

		if (static_cpu_has(X86_FEATURE_CLFLUSH_MONITOR)) {

		if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {

			mb();

			mb();

			clflush((void *)&current_thread_info()->flags);

			clflush((void *)&current_thread_info()->flags);

			mb();

			mb();

arch/x86/include/uapi/asm/msr-index.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -297,6 +297,8 @@ 
#define MSR_IA32_TSC_ADJUST             0x0000003b

#define MSR_IA32_TSC_ADJUST             0x0000003b

#define MSR_IA32_BNDCFGS		0x00000d90

#define MSR_IA32_BNDCFGS		0x00000d90





#define MSR_IA32_XSS			0x00000da0



#define FEATURE_CONTROL_LOCKED				(1<<0)

#define FEATURE_CONTROL_LOCKED				(1<<0)

#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)

#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)

#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)

#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)