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Commit e8ec9c23 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: ipa: Update IPA register offsets and fields"

parents 35a14d25 b8aa4a8d

drivers/platform/msm/ipa/ipa_v3/ipa_interrupts.c

+3 −0
Original line number Diff line number Diff line
@@ -63,6 +63,9 @@ static int ipa3_irq_mapping[IPA_IRQ_MAX] = { 
	[IPA_GSI_IPA_IF_TLV_RCVD_IRQ]		= 24,

	[IPA_GSI_UC_IRQ]			= 25,

	[IPA_TLV_LEN_MIN_DSM_IRQ]		= 26,

	[IPA_DRBIP_PKT_EXCEED_MAX_SIZE_IRQ]	= 27,

	[IPA_DRBIP_DATA_SCTR_CFG_ERROR_IRQ]	= 28,

	[IPA_DRBIP_IMM_CMD_NO_FLSH_HZRD_IRQ]	= 29,

};



static void ipa3_interrupt_defer(struct work_struct *work);

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+34 −23
Original line number Diff line number Diff line
@@ -661,33 +661,36 @@ enum ipa_qmb_instance_type { 
struct ipa_qmb_outstanding {

	u16 ot_reads;

	u16 ot_writes;

	u16 ot_read_beats;

};



/*TODO: Update correct values of max_read_beats for all targets*/



static const struct ipa_qmb_outstanding ipa3_qmb_outstanding

		[IPA_VER_MAX][IPA_QMB_INSTANCE_MAX] = {

	[IPA_3_0][IPA_QMB_INSTANCE_DDR]	= {8, 8},

	[IPA_3_0][IPA_QMB_INSTANCE_PCIE]	= {8, 2},

	[IPA_3_5][IPA_QMB_INSTANCE_DDR]	= {8, 8},

	[IPA_3_5][IPA_QMB_INSTANCE_PCIE]	= {12, 4},

	[IPA_3_5_MHI][IPA_QMB_INSTANCE_DDR]	= {8, 8},

	[IPA_3_5_MHI][IPA_QMB_INSTANCE_PCIE]	= {12, 4},

	[IPA_3_5_1][IPA_QMB_INSTANCE_DDR]	= {8, 8},

	[IPA_3_5_1][IPA_QMB_INSTANCE_PCIE]	= {12, 4},

	[IPA_4_0][IPA_QMB_INSTANCE_DDR]	= {12, 8},

	[IPA_4_0][IPA_QMB_INSTANCE_PCIE]	= {12, 4},

	[IPA_4_0_MHI][IPA_QMB_INSTANCE_DDR]	= {12, 8},

	[IPA_4_0_MHI][IPA_QMB_INSTANCE_PCIE]	= {12, 4},

	[IPA_4_1][IPA_QMB_INSTANCE_DDR]	= {12, 8},

	[IPA_4_1][IPA_QMB_INSTANCE_PCIE]	= {12, 4},

	[IPA_4_2][IPA_QMB_INSTANCE_DDR]	= {12, 8},

	[IPA_4_5][IPA_QMB_INSTANCE_DDR]	= {16, 8},

	[IPA_4_5][IPA_QMB_INSTANCE_PCIE]	= {12, 8},

	[IPA_4_5_MHI][IPA_QMB_INSTANCE_DDR]	= {16, 8},

	[IPA_4_5_MHI][IPA_QMB_INSTANCE_PCIE]	= {12, 8},

	[IPA_4_5_APQ][IPA_QMB_INSTANCE_DDR]	= {16, 8},

	[IPA_4_5_APQ][IPA_QMB_INSTANCE_PCIE]	= {12, 8},

	[IPA_4_7][IPA_QMB_INSTANCE_DDR]	        = {13, 12},

	[IPA_4_9][IPA_QMB_INSTANCE_DDR]	        = {16, 8},

	[IPA_3_0][IPA_QMB_INSTANCE_DDR]		= {8, 8, 0},

	[IPA_3_0][IPA_QMB_INSTANCE_PCIE]	= {8, 2, 0},

	[IPA_3_5][IPA_QMB_INSTANCE_DDR]		= {8, 8, 0},

	[IPA_3_5][IPA_QMB_INSTANCE_PCIE]	= {12, 4, 0},

	[IPA_3_5_MHI][IPA_QMB_INSTANCE_DDR]	= {8, 8, 0},

	[IPA_3_5_MHI][IPA_QMB_INSTANCE_PCIE]	= {12, 4, 0},

	[IPA_3_5_1][IPA_QMB_INSTANCE_DDR]	= {8, 8, 0},

	[IPA_3_5_1][IPA_QMB_INSTANCE_PCIE]	= {12, 4, 0},

	[IPA_4_0][IPA_QMB_INSTANCE_DDR]		= {12, 8, 120},

	[IPA_4_0][IPA_QMB_INSTANCE_PCIE]	= {12, 4, 0},

	[IPA_4_0_MHI][IPA_QMB_INSTANCE_DDR]	= {12, 8, 0},

	[IPA_4_0_MHI][IPA_QMB_INSTANCE_PCIE]	= {12, 4, 0},

	[IPA_4_1][IPA_QMB_INSTANCE_DDR]		= {12, 8, 120},

	[IPA_4_1][IPA_QMB_INSTANCE_PCIE]	= {12, 4, 0},

	[IPA_4_2][IPA_QMB_INSTANCE_DDR]		= {12, 8, 0},

	[IPA_4_5][IPA_QMB_INSTANCE_DDR]		= {16, 8, 120},

	[IPA_4_5][IPA_QMB_INSTANCE_PCIE]	= {12, 8, 0},

	[IPA_4_5_MHI][IPA_QMB_INSTANCE_DDR]	= {16, 8, 120},

	[IPA_4_5_MHI][IPA_QMB_INSTANCE_PCIE]	= {12, 8, 0},

	[IPA_4_5_APQ][IPA_QMB_INSTANCE_DDR]	= {16, 8, 120},

	[IPA_4_5_APQ][IPA_QMB_INSTANCE_PCIE]	= {12, 8, 0},

	[IPA_4_7][IPA_QMB_INSTANCE_DDR]	        = {13, 12, 120},

	[IPA_4_9][IPA_QMB_INSTANCE_DDR]	        = {16, 8, 120},

};



struct ipa_ep_configuration {
@@ -4150,9 +4153,17 @@ static void ipa3_cfg_qsb(void) 


	hw_type_idx = ipa3_get_hw_type_index();



	/*

	 * Read the register values before writing to them to ensure

	 * other values are not overwritten

	 */

	ipahal_read_reg_fields(IPA_QSB_MAX_WRITES, &max_writes);

	ipahal_read_reg_fields(IPA_QSB_MAX_READS, &max_reads);



	qmb_ot = &(ipa3_qmb_outstanding[hw_type_idx][IPA_QMB_INSTANCE_DDR]);

	max_reads.qmb_0_max_reads = qmb_ot->ot_reads;

	max_writes.qmb_0_max_writes = qmb_ot->ot_writes;

	max_reads.qmb_0_max_read_beats = qmb_ot->ot_read_beats;



	qmb_ot = &(ipa3_qmb_outstanding[hw_type_idx][IPA_QMB_INSTANCE_PCIE]);

	max_reads.qmb_1_max_reads = qmb_ot->ot_reads;

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c

+324 −17
Original line number Diff line number Diff line
@@ -947,10 +947,6 @@ static void ipareg_parse_timers_xo_clk_div_cfg( 
static void ipareg_construct_comp_cfg_comon(

	const struct ipahal_reg_comp_cfg *comp_cfg, u32 *val)

{

	IPA_SETFIELD_IN_REG(*val,

		comp_cfg->ipa_atomic_fetcher_arb_lock_dis,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK);



	IPA_SETFIELD_IN_REG(*val,

		!!comp_cfg->ipa_qmb_select_by_address_global_en,
@@ -1036,6 +1032,11 @@ static void ipareg_construct_comp_cfg( 


	ipareg_construct_comp_cfg_comon(comp_cfg, val);



	IPA_SETFIELD_IN_REG(*val,

		comp_cfg->ipa_atomic_fetcher_arb_lock_dis,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK);



	IPA_SETFIELD_IN_REG(*val,

		!!comp_cfg->enable,

		IPA_COMP_CFG_ENABLE_SHFT,
@@ -1055,21 +1056,73 @@ static void ipareg_construct_comp_cfg_v4_5( 


	ipareg_construct_comp_cfg_comon(comp_cfg, val);



	IPA_SETFIELD_IN_REG(*val,

		comp_cfg->ipa_atomic_fetcher_arb_lock_dis,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK);



	IPA_SETFIELD_IN_REG(*val,

		!!comp_cfg->ipa_full_flush_wait_rsc_closure_en,

		IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_5,

		IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_5);

}



static void ipareg_construct_comp_cfg_v4_9(

	enum ipahal_reg_name reg, const void *fields, u32 *val)

{

	struct ipahal_reg_comp_cfg *comp_cfg =

		(struct ipahal_reg_comp_cfg *)fields;



	ipareg_construct_comp_cfg_comon(comp_cfg, val);



	IPA_SETFIELD_IN_REG(*val,

		!!comp_cfg->gen_qmb_0_dynamic_asize,

		IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v4_9,

		IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v4_9);



	IPA_SETFIELD_IN_REG(*val,

		!!comp_cfg->gen_qmb_1_dynamic_asize,

		IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v4_9,

		IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v4_9);



	IPA_SETFIELD_IN_REG(*val,

		!!comp_cfg->ipa_atomic_fetcher_arb_lock_dis,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v4_9,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v4_9);



	IPA_SETFIELD_IN_REG(*val,

	!!comp_cfg->gsi_if_out_of_buf_stop_reset_mask_enable,

	IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v4_9,

	IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v4_9);



	IPA_SETFIELD_IN_REG(*val,

		!!comp_cfg->genqmb_aooowr,

		IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v4_9,

		IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v4_9);



	IPA_SETFIELD_IN_REG(*val,

		!!comp_cfg->qmb_ram_rd_cache_disable,

		IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v4_9,

		IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v4_9);



	IPA_SETFIELD_IN_REG(*val,

		!!comp_cfg->ipa_full_flush_wait_rsc_closure_en,

		IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_9,

		IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_9);



	IPA_SETFIELD_IN_REG(*val,

	!!comp_cfg->ram_arb_priority_client_samp_fix_disable,

	IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v4_9,

	IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v4_9);





}



static void ipareg_parse_comp_cfg_common(

	struct ipahal_reg_comp_cfg *comp_cfg, u32 val)

{

	memset(comp_cfg, 0, sizeof(struct ipahal_reg_comp_cfg));



	comp_cfg->ipa_atomic_fetcher_arb_lock_dis =

		IPA_GETFIELD_FROM_REG(val,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK);



	comp_cfg->ipa_qmb_select_by_address_global_en =

		IPA_GETFIELD_FROM_REG(val,
@@ -1155,6 +1208,11 @@ static void ipareg_parse_comp_cfg( 


	ipareg_parse_comp_cfg_common(comp_cfg, val);



	comp_cfg->ipa_atomic_fetcher_arb_lock_dis =

		IPA_GETFIELD_FROM_REG(val,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK);



	comp_cfg->enable =

		IPA_GETFIELD_FROM_REG(val,

		IPA_COMP_CFG_ENABLE_SHFT,
@@ -1174,12 +1232,67 @@ static void ipareg_parse_comp_cfg_v4_5( 


	ipareg_parse_comp_cfg_common(comp_cfg, val);



	comp_cfg->ipa_atomic_fetcher_arb_lock_dis =

		IPA_GETFIELD_FROM_REG(val,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK);



	comp_cfg->ipa_full_flush_wait_rsc_closure_en =

		IPA_GETFIELD_FROM_REG(val,

		IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_5,

		IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_5);

}



static void ipareg_parse_comp_cfg_v4_9(

	enum ipahal_reg_name reg, void *fields, u32 val)

{

	struct ipahal_reg_comp_cfg *comp_cfg =

		(struct ipahal_reg_comp_cfg *)fields;



	ipareg_parse_comp_cfg_common(comp_cfg, val);



	comp_cfg->gen_qmb_0_dynamic_asize =

		IPA_GETFIELD_FROM_REG(val,

		IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v4_9,

		IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v4_9);



	comp_cfg->gen_qmb_1_dynamic_asize =

		IPA_GETFIELD_FROM_REG(val,

		IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v4_9,

		IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v4_9);



	comp_cfg->ipa_atomic_fetcher_arb_lock_dis =

		IPA_GETFIELD_FROM_REG(val,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v4_9,

		IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v4_9);



	comp_cfg->gsi_if_out_of_buf_stop_reset_mask_enable =

	IPA_GETFIELD_FROM_REG(val,

	IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v4_9,

	IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v4_9);



	comp_cfg->genqmb_aooowr =

		IPA_GETFIELD_FROM_REG(val,

		IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v4_9,

		IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v4_9);



	comp_cfg->qmb_ram_rd_cache_disable =

		IPA_GETFIELD_FROM_REG(val,

		IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v4_9,

		IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v4_9);



	comp_cfg->ipa_full_flush_wait_rsc_closure_en =

		IPA_GETFIELD_FROM_REG(val,

		IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_9,

		IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_9);



	comp_cfg->ram_arb_priority_client_samp_fix_disable =

	IPA_GETFIELD_FROM_REG(val,

	IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v4_9,

	IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v4_9);



}



static void ipareg_parse_state_tx_wrapper_v4_5(

	enum ipahal_reg_name reg, void *fields, u32 val)

{
@@ -1470,6 +1583,17 @@ static void ipareg_construct_endp_init_rsrc_grp_n_v4_5( 
		IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_5);

}



static void ipareg_construct_endp_init_rsrc_grp_n_v4_9(

		enum ipahal_reg_name reg, const void *fields, u32 *val)

{

	struct ipahal_reg_endp_init_rsrc_grp *rsrc_grp =

		(struct ipahal_reg_endp_init_rsrc_grp *)fields;



	IPA_SETFIELD_IN_REG(*val, rsrc_grp->rsrc_grp,

		IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_9,

		IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_9);

}



static void ipareg_construct_endp_init_hdr_metadata_n(

		enum ipahal_reg_name reg, const void *fields, u32 *val)

{
@@ -2022,14 +2146,11 @@ static void ipareg_construct_endp_init_hdr_n(enum ipahal_reg_name reg, 
		IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK);

}



static void ipareg_construct_endp_init_hdr_n_v4_5(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

static void ipareg_construct_endp_init_hdr_n_common(

	struct ipa_ep_cfg_hdr *ep_hdr, u32 *val)

{

	struct ipa_ep_cfg_hdr *ep_hdr;

	u32 msb;



	ep_hdr = (struct ipa_ep_cfg_hdr *)fields;



	msb = ep_hdr->hdr_ofst_metadata >>

		hweight_long(IPA_ENDP_INIT_HDR_n_HDR_OFST_METADATA_BMSK_v4_5);

	IPA_SETFIELD_IN_REG(*val, msb,
@@ -2046,10 +2167,6 @@ static void ipareg_construct_endp_init_hdr_n_v4_5(enum ipahal_reg_name reg, 
		IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_LEN_INC_DEAGG_HDR_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_a5_mux,

		IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK_v4_5);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_ofst_pkt_size,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_OFST_PKT_SIZE_BMSK_v4_5);
@@ -2075,6 +2192,32 @@ static void ipareg_construct_endp_init_hdr_n_v4_5(enum ipahal_reg_name reg, 
		IPA_ENDP_INIT_HDR_n_HDR_LEN_BMSK_v4_5);

}



static void ipareg_construct_endp_init_hdr_n_v4_5(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{

	struct ipa_ep_cfg_hdr *ep_hdr;



	ep_hdr = (struct ipa_ep_cfg_hdr *)fields;



	ipareg_construct_endp_init_hdr_n_common(ep_hdr, val);



	IPA_SETFIELD_IN_REG(*val, ep_hdr->hdr_a5_mux,

		IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_SHFT_v4_5,

		IPA_ENDP_INIT_HDR_n_HDR_A5_MUX_BMSK_v4_5);



}



static void ipareg_construct_endp_init_hdr_n_v4_9(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{

	struct ipa_ep_cfg_hdr *ep_hdr;



	ep_hdr = (struct ipa_ep_cfg_hdr *)fields;



	ipareg_construct_endp_init_hdr_n_common(ep_hdr, val);



}



static void ipareg_construct_route(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{
@@ -2158,6 +2301,42 @@ static void ipareg_construct_qsb_max_reads_v4_0(enum ipahal_reg_name reg, 
		    IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_BMSK_V4_0);

}



static void ipareg_parse_qsb_max_reads(enum ipahal_reg_name reg,

	void *fields, u32 val)

{

	struct ipahal_reg_qsb_max_reads *max_reads;



	max_reads = (struct ipahal_reg_qsb_max_reads *)fields;



	max_reads->qmb_0_max_reads = IPA_GETFIELD_FROM_REG(val,

			    IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_SHFT,

			    IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BMSK);

	max_reads->qmb_1_max_reads = IPA_GETFIELD_FROM_REG(val,

			    IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_SHFT,

			    IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BMSK);

	max_reads->qmb_0_max_read_beats = IPA_GETFIELD_FROM_REG(val,

		    IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_SHFT_V4_0,

		    IPA_QSB_MAX_READS_GEN_QMB_0_MAX_READS_BEATS_BMSK_V4_0);

	max_reads->qmb_1_max_read_beats = IPA_GETFIELD_FROM_REG(val,

		    IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_SHFT_V4_0,

		    IPA_QSB_MAX_READS_GEN_QMB_1_MAX_READS_BEATS_BMSK_V4_0);

}



static void ipareg_parse_qsb_max_writes(enum ipahal_reg_name reg,

	void *fields, u32 val)

{

	struct ipahal_reg_qsb_max_writes *max_writes;



	max_writes = (struct ipahal_reg_qsb_max_writes *)fields;



	max_writes->qmb_0_max_writes = IPA_GETFIELD_FROM_REG(val,

			    IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_SHFT,

			    IPA_QSB_MAX_WRITES_GEN_QMB_0_MAX_WRITES_BMSK);

	max_writes->qmb_1_max_writes = IPA_GETFIELD_FROM_REG(val,

			    IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_SHFT,

			    IPA_QSB_MAX_WRITES_GEN_QMB_1_MAX_WRITES_BMSK);

}



static void ipareg_parse_tx_cfg(enum ipahal_reg_name reg,

	void *fields, u32 val)

{
@@ -2227,6 +2406,20 @@ static void ipareg_parse_tx_cfg_v4_5(enum ipahal_reg_name reg, 
		IPA_TX_CFG_DUAL_TX_ENABLE_BMSK_V4_5);

}



static void ipareg_parse_tx_cfg_v4_9(enum ipahal_reg_name reg,

	void *fields, u32 val)

{

	struct ipahal_reg_tx_cfg *tx_cfg;



	ipareg_parse_tx_cfg_v4_5(reg, fields, val);



	tx_cfg = (struct ipahal_reg_tx_cfg *)fields;



	tx_cfg->sspnd_pa_no_start_state = IPA_GETFIELD_FROM_REG(val,

		IPA_TX_CFG_SSPND_PA_NO_START_STATE_SHFT_V4_9,

		IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK_V4_9);

}



static void ipareg_construct_tx_cfg(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{
@@ -2297,6 +2490,20 @@ static void ipareg_construct_tx_cfg_v4_5(enum ipahal_reg_name reg, 
		IPA_TX_CFG_DUAL_TX_ENABLE_BMSK_V4_5);

}



static void ipareg_construct_tx_cfg_v4_9(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{

	struct ipahal_reg_tx_cfg *tx_cfg;



	ipareg_construct_tx_cfg_v4_5(reg, fields, val);



	tx_cfg = (struct ipahal_reg_tx_cfg *)fields;



	IPA_SETFIELD_IN_REG(*val, tx_cfg->sspnd_pa_no_start_state,

		IPA_TX_CFG_SSPND_PA_NO_START_STATE_SHFT_V4_9,

		IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK_V4_9);

}



static void ipareg_construct_idle_indication_cfg(enum ipahal_reg_name reg,

	const void *fields, u32 *val)

{
@@ -3279,6 +3486,106 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = { 
	[IPA_HW_v4_7][IPA_STATE_TX_WRAPPER] = {

		ipareg_construct_dummy, ipareg_parse_state_tx_wrapper_v4_7,

		0x00000090, 0, 0, 0, 1 },



	/* IPA4.9 */



	/*IPA_DEBUG*/

	[IPA_HW_v4_9][IPA_ENDP_GSI_CFG1_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x000026C0, 0x4, 0, 30, 0 },

	[IPA_HW_v4_9][IPA_ENDP_GSI_CFG_TLV_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00002758, 0x4, 0, 30, 0 },

	[IPA_HW_v4_9][IPA_ENDP_GSI_CFG_AOS_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x000027D4, 0x4, 0, 30, 0 },





	/*IPA_CFG*/

	[IPA_HW_v4_9][IPA_COMP_CFG] = {

		ipareg_construct_comp_cfg_v4_9, ipareg_parse_comp_cfg_v4_9,

		0x0000003C, 0, 0, 0, 0},

	[IPA_HW_v4_9][IPA_QSB_MAX_READS] = {

		ipareg_construct_qsb_max_reads_v4_0, ipareg_parse_qsb_max_reads,

		0x00000078, 0, 0, 0, 0},

	[IPA_HW_v4_9][IPA_QSB_MAX_WRITES] = {

		ipareg_construct_qsb_max_writes, ipareg_parse_qsb_max_writes,

		0x00000074, 0, 0, 0, 0},

	[IPA_HW_v4_9][IPA_TX_CFG] = {

		ipareg_construct_tx_cfg_v4_9, ipareg_parse_tx_cfg_v4_9,

		0x000001FC, 0, 0, 0, 0},

	[IPA_HW_v4_9][IPA_ENDP_INIT_NAT_n] = {

		ipareg_construct_endp_init_nat_n, ipareg_parse_dummy,

		0x0000080C, 0x70, 0, 10, 0},

	[IPA_HW_v4_9][IPA_ENDP_INIT_HDR_n] = {

		ipareg_construct_endp_init_hdr_n_v4_9, ipareg_parse_dummy,

		0x00000810, 0x70, 0, 30, 0},

	[IPA_HW_v4_9][IPA_ENDP_INIT_HDR_METADATA_n] = {

		ipareg_construct_endp_init_hdr_metadata_n,

		ipareg_parse_dummy,

		0x0000081c, 0x70, 0, 10, 0},

	[IPA_HW_v4_9][IPA_ENDP_INIT_MODE_n] = {

		ipareg_construct_endp_init_mode_n_v4_5, ipareg_parse_dummy,

		0x00000820, 0x70, 0, 10, 0},

	[IPA_HW_v4_9][IPA_ENDP_INIT_DEAGGR_n] = {

		ipareg_construct_endp_init_deaggr_n,

		ipareg_parse_dummy,

		0x00000834, 0x70, 0, 10, 0},

	[IPA_HW_v4_9][IPA_ENDP_INIT_RSRC_GRP_n] = {

		ipareg_construct_endp_init_rsrc_grp_n_v4_9,

		ipareg_parse_dummy,

		0x00000838, 0x70, 0, 30, 0},

	[IPA_HW_v4_9][IPA_ENDP_INIT_SEQ_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x0000083C, 0x70, 0, 10, 0},

	[IPA_HW_v4_9][IPA_ENDP_INIT_CONN_TRACK_n] = {

		ipareg_construct_endp_init_conn_track_n,

		ipareg_parse_dummy,

		0x00000850, 0x70, 0, 10, 0},



	/*IPA_EE*/

	[IPA_HW_v4_9][IPA_IRQ_STTS_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00004008, 0x1000, 0, 0, 0},

	[IPA_HW_v4_9][IPA_IRQ_EN_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x0000400c, 0x1000, 0, 0, 0},

	[IPA_HW_v4_9][IPA_IRQ_CLR_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00004010, 0x1000, 0, 0, 0},

	[IPA_HW_v4_9][IPA_SNOC_FEC_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00004018, 0x1000, 0, 0, 0},

	[IPA_HW_v4_9][IPA_SUSPEND_IRQ_INFO_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00004030, 0x1000, 0, 0, 0},

	[IPA_HW_v4_9][IPA_SUSPEND_IRQ_EN_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00004034, 0x1000, 0, 0, 0},

	[IPA_HW_v4_9][IPA_SUSPEND_IRQ_CLR_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00004038, 0x1000, 0, 0, 0},

	[IPA_HW_v4_9][IPA_HOLB_DROP_IRQ_INFO_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x0000403C, 0x1000, 0, 0, 0},

	[IPA_HW_v4_9][IPA_HOLB_DROP_IRQ_EN_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00004040, 0x1000, 0, 0, 0},

	[IPA_HW_v4_9][IPA_HOLB_DROP_IRQ_CLR_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00004044, 0x1000, 0, 0, 0},

	[IPA_HW_v4_9][IPA_IRQ_EE_UC_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x0000401c, 0x1000, 0, 0, 1},

	[IPA_HW_v4_9][IPA_FEC_ADDR_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00004020, 0x1000, 0, 0, 1},

	[IPA_HW_v4_9][IPA_FEC_ADDR_MSB_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00004024, 0x1000, 0, 0, 1},

	[IPA_HW_v4_9][IPA_FEC_ATTR_EE_n] = {

		ipareg_construct_dummy, ipareg_parse_dummy,

		0x00004028, 0x1000, 0, 0, 1},

};



/*

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h

+11 −0
Original line number Diff line number Diff line
@@ -358,8 +358,13 @@ struct ipahal_reg_timers_xo_clk_div_cfg { 
 * @ipa_full_flush_wait_rsc_closure_en: relevant starting IPA4.5

 */

struct ipahal_reg_comp_cfg {

	bool gen_qmb_0_dynamic_asize;

	bool gen_qmb_1_dynamic_asize;

	bool ipa_full_flush_wait_rsc_closure_en;

	u8 ipa_atomic_fetcher_arb_lock_dis;

	bool gsi_if_out_of_buf_stop_reset_mask_enable;

	bool genqmb_aooowr;

	bool qmb_ram_rd_cache_disable;

	bool ipa_qmb_select_by_address_global_en;

	bool gsi_multi_axi_masters_dis;

	bool gsi_snoc_cnoc_loop_protection_disable;
@@ -376,6 +381,7 @@ struct ipahal_reg_comp_cfg { 
	bool gen_qmb_1_snoc_bypass_dis;

	bool gen_qmb_0_snoc_bypass_dis;

	bool gsi_snoc_bypass_dis;

	bool ram_arb_priority_client_samp_fix_disable;

	bool enable;

};
@@ -610,6 +616,10 @@ struct ipahal_reg_qsb_max_reads { 
 * @dmaw_scnd_outsd_pred_en:

 * @pa_mask_en:

 * @dual_tx_enable: When 1 TX0 and TX1 are enabled. When 0 only TX0 is enabled

 * @sspnd_pa_no_start_state: When 1 sspnd_req does not take inco account

			     PA FSM state START.

			     When 0 sspnd_req_ will not be answered

			     on that state.

 *  Relevant starting IPA4.5

 */

struct ipahal_reg_tx_cfg {
@@ -622,6 +632,7 @@ struct ipahal_reg_tx_cfg { 
	u32 dmaw_scnd_outsd_pred_en;

	u32 pa_mask_en;

	bool dual_tx_enable;

	bool sspnd_pa_no_start_state;

};



/*

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h

+23 −0
Original line number Diff line number Diff line
@@ -263,6 +263,8 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v3_5 0

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_5 0x7

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_5 0

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_BMSK_v4_9 0x3

#define IPA_ENDP_INIT_RSRC_GRP_n_RSRC_GRP_SHFT_v4_9 0



/* IPA_SHARED_MEM_SIZE register */

#define IPA_SHARED_MEM_SIZE_SHARED_MEM_BADDR_BMSK 0xffff0000
@@ -495,6 +497,8 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_BMSK_V3_5 (0x1C)

#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_SHFT_V3_5 (2)



#define IPA_TX_CFG_SSPND_PA_NO_START_STATE_BMSK_V4_9 (0x40000)

#define IPA_TX_CFG_SSPND_PA_NO_START_STATE_SHFT_V4_9 (0x12)

#define IPA_TX_CFG_DUAL_TX_ENABLE_BMSK_V4_5 (0x20000)

#define IPA_TX_CFG_DUAL_TX_ENABLE_SHFT_V4_5 (0x11)

#define IPA_TX_CFG_PREFETCH_ALMOST_EMPTY_SIZE_TX1_BMSK_V4_0 (0x1e000)
@@ -604,6 +608,25 @@ int ipahal_reg_init(enum ipa_hw_type ipa_hw_type); 
#define IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK_v4_5 0x2

#define IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT_v4_5 1





/*IPA 4.9*/

#define IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_BMSK_v4_9 0x80000000

#define IPA_COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE_SHFT_v4_9 31

#define IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_BMSK_v4_9 0x40000000

#define IPA_COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE_SHFT_v4_9 30

#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK_v4_9 0x1C00000

#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT_v4_9 22

#define IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_BMSK_v4_9 0x200000

#define IPA_COMP_CFG_GSI_IF_OUT_OF_BUF_STOP_RESET_MASK_ENABLE_SHFT_v4_9 21

#define IPA_COMP_CFG_GENQMB_AOOOWR_BMSK_v4_9 0x100000

#define IPA_COMP_CFG_GENQMB_AOOOWR_SHFT_v4_9 20

#define IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_BMSK_v4_9 0x80000

#define IPA_COMP_CFG_QMB_RAM_RD_CACHE_DISABLE_SHFT_v4_9 19

#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_BMSK_v4_9 0x20000

#define IPA_COMP_CFG_IPA_FULL_FLUSH_WAIT_RSC_CLOSURE_EN_SHFT_v4_9 17

#define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_BMSK_v4_9 0x1

#define IPA_COMP_CFG_RAM_ARB_PRIORITY_CLIENT_SAMP_FIX_DISABLE_SHFT_v4_9 0



/* IPA_COAL registers*/

#define IPA_STATE_COAL_MASTER_VP_TIMER_EXPIRED_BMSK 0xF0000000

#define IPA_STATE_COAL_MASTER_VP_TIMER_EXPIRED_SHFT 28