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Commit e8b50608 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_fixes_5.0_3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS fixes from Paul Burton:
 "A batch of MIPS fixes for 5.0, nothing too scary.

   - A workaround for a Loongson 3 CPU bug is the biggest change, but
     still fairly straightforward. It adds extra memory barriers (sync
     instructions) around atomics to avoid a CPU bug that can break
     atomicity.

   - Loongson64 also sees a fix for powering off some systems which
     would incorrectly reboot rather than waiting for the power down
     sequence to complete.

   - We have DT fixes for the Ingenic JZ4740 SoC & the JZ4780-based Ci20
     board, and a DT warning fix for the Nexsys4/MIPSfpga board.

   - The Cavium Octeon platform sees a further fix to the behaviour of
     the pcie_disable command line argument that was introduced in v3.3.

   - The VDSO, introduced in v4.4, sees build fixes for configurations
     of GCC that were built using the --with-fp-32= flag to specify a
     default 32-bit floating point ABI.

   - get_frame_info() sees a fix for configurations with
     CONFIG_KALLSYMS=n, for which it previously always returned an
     error.

   - If the MIPS Coherence Manager (CM) reports an error then we'll now
     clear that error correctly so that the GCR_ERROR_CAUSE register
     will be updated with information about any future errors"

* tag 'mips_fixes_5.0_3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  mips: cm: reprime error cause
  mips: loongson64: remove unreachable(), fix loongson_poweroff().
  MIPS: Remove function size check in get_frame_info()
  MIPS: Use lower case for addresses in nexys4ddr.dts
  MIPS: Loongson: Introduce and use loongson_llsc_mb()
  MIPS: VDSO: Include $(ccflags-vdso) in o32,n32 .lds builds
  MIPS: VDSO: Use same -m%-float cflag as the kernel proper
  MIPS: OCTEON: don't set octeon_dma_bar_type if PCI is disabled
  DTS: CI20: Fix bugs in ci20's device tree.
  MIPS: DTS: jz4740: Correct interrupt number of DMA core
parents e5a8a116 05dc6001

arch/mips/Kconfig

+15 −0
Original line number Diff line number Diff line
@@ -1403,6 +1403,21 @@ config LOONGSON3_ENHANCEMENT 
	  please say 'N' here. If you want a high-performance kernel to run on

	  new Loongson 3 machines only, please say 'Y' here.



config CPU_LOONGSON3_WORKAROUNDS

	bool "Old Loongson 3 LLSC Workarounds"

	default y if SMP

	depends on CPU_LOONGSON3

	help

	  Loongson 3 processors have the llsc issues which require workarounds.

	  Without workarounds the system may hang unexpectedly.



	  Newer Loongson 3 will fix these issues and no workarounds are needed.

	  The workarounds have no significant side effect on them but may

	  decrease the performance of the system so this option should be

	  disabled unless the kernel is intended to be run on old systems.



	  If unsure, please say Y.



config CPU_LOONGSON2E

	bool "Loongson 2E"

	depends on SYS_HAS_CPU_LOONGSON2E

arch/mips/boot/dts/ingenic/ci20.dts

+4 −4
Original line number Diff line number Diff line
@@ -76,7 +76,7 @@ 
	status = "okay";



	pinctrl-names = "default";

	pinctrl-0 = <&pins_uart2>;

	pinctrl-0 = <&pins_uart3>;

};



&uart4 {
@@ -196,9 +196,9 @@ 
		bias-disable;

	};



	pins_uart2: uart2 {

		function = "uart2";

		groups = "uart2-data", "uart2-hwflow";

	pins_uart3: uart3 {

		function = "uart3";

		groups = "uart3-data", "uart3-hwflow";

		bias-disable;

	};

arch/mips/boot/dts/ingenic/jz4740.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -161,7 +161,7 @@ 
		#dma-cells = <2>;



		interrupt-parent = <&intc>;

		interrupts = <29>;

		interrupts = <20>;



		clocks = <&cgu JZ4740_CLK_DMA>;

arch/mips/boot/dts/xilfpga/nexys4ddr.dts

+4 −4
Original line number Diff line number Diff line
@@ -90,11 +90,11 @@ 
		interrupts = <0>;

	};



	axi_i2c: i2c@10A00000 {

	axi_i2c: i2c@10a00000 {

	    compatible = "xlnx,xps-iic-2.00.a";

	    interrupt-parent = <&axi_intc>;

	    interrupts = <4>;

	    reg = < 0x10A00000 0x10000 >;

	    reg = < 0x10a00000 0x10000 >;

	    clocks = <&ext>;

	    xlnx,clk-freq = <0x5f5e100>;

	    xlnx,family = "Artix7";
@@ -106,9 +106,9 @@ 
	    #address-cells = <1>;

	    #size-cells = <0>;



	    ad7420@4B {

	    ad7420@4b {

		compatible = "adi,adt7420";

		reg = <0x4B>;

		reg = <0x4b>;

	    };

	} ;

};

arch/mips/include/asm/atomic.h

+6 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ static __inline__ void atomic_##op(int i, atomic_t * v) \ 
	if (kernel_uses_llsc) {						      \

		int temp;						      \

									      \

		loongson_llsc_mb();					      \

		__asm__ __volatile__(					      \

		"	.set	push					\n"   \

		"	.set	"MIPS_ISA_LEVEL"			\n"   \
@@ -85,6 +86,7 @@ static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \ 
	if (kernel_uses_llsc) {						      \

		int temp;						      \

									      \

		loongson_llsc_mb();					      \

		__asm__ __volatile__(					      \

		"	.set	push					\n"   \

		"	.set	"MIPS_ISA_LEVEL"			\n"   \
@@ -118,6 +120,7 @@ static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \ 
	if (kernel_uses_llsc) {						      \

		int temp;						      \

									      \

		loongson_llsc_mb();					      \

		__asm__ __volatile__(					      \

		"	.set	push					\n"   \

		"	.set	"MIPS_ISA_LEVEL"			\n"   \
@@ -256,6 +259,7 @@ static __inline__ void atomic64_##op(long i, atomic64_t * v) \ 
	if (kernel_uses_llsc) {						      \

		long temp;						      \

									      \

		loongson_llsc_mb();					      \

		__asm__ __volatile__(					      \

		"	.set	push					\n"   \

		"	.set	"MIPS_ISA_LEVEL"			\n"   \
@@ -283,6 +287,7 @@ static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v) \ 
	if (kernel_uses_llsc) {						      \

		long temp;						      \

									      \

		loongson_llsc_mb();					      \

		__asm__ __volatile__(					      \

		"	.set	push					\n"   \

		"	.set	"MIPS_ISA_LEVEL"			\n"   \
@@ -316,6 +321,7 @@ static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v) \ 
	if (kernel_uses_llsc) {						      \

		long temp;						      \

									      \

		loongson_llsc_mb();					      \

		__asm__ __volatile__(					      \

		"	.set	push					\n"   \

		"	.set	"MIPS_ISA_LEVEL"			\n"   \