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Commit e865e79e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add initial device tree for SCUBA"

parents b34dadd8 26ab3586

qcom/Makefile

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@@ -227,6 +227,8 @@ else 
dtb-$(CONFIG_ARCH_MONACO) += monaco-rumi.dtb

endif



dtb-$(CONFIG_ARCH_SCUBA) += qrb2210-rb1.dtb



ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)

ifeq ($(CONFIG_AUTO_LXC_OVERLAY), y)

	dtbo-$(CONFIG_ARCH_SA8155) += \

qcom/msm-arm-smmu-qrb2210-rb1.dtsi

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#include <dt-bindings/interrupt-controller/arm-gic.h>



&soc {

	kgsl_smmu: kgsl-smmu@0x59a0000 {

		compatible = "qcom,qsmmu-v500";

		reg = <0x59a0000 0x10000>,

			<0x59c2000 0x20>;

		reg-names = "base", "tcu-base";

		#iommu-cells = <2>;

		qcom,skip-init;

		qcom,no-dynamic-asid;

		qcom,use-3-lvl-tables;

		#global-interrupts = <1>;

		qcom,regulator-names = "vdd";

		#size-cells = <1>;

		ranges;

		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,

			<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;



			qcom,actlr =

				/* ALL CBs of GFX: +15 deep PF */

				<0x0 0x3ff 0x30B>;



		gfx_0_tbu: gfx_0_tbu@0x59c5000 {

				compatible = "qcom,qsmmuv500-tbu";

				reg = <0x59c5000 0x1000>,

					<0x59c2200 0x8>;

				reg-names = "base", "status-reg";

				qcom,stream-id-range = <0x0 0x400>;

				interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;

		};

	};



	apps_smmu: apps-smmu@0xc600000 {

				compatible = "qcom,qsmmu-v500";

				reg = <0xc600000 0x80000>,

					<0xc782000 0x20>;

				reg-names = "base", "tcu-base";

				#iommu-cells = <2>;

				qcom,skip-init;

				qcom,use-3-lvl-tables;

				#global-interrupts = <1>;

				#size-cells = <1>;

				#address-cells = <1>;

				ranges;

				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;

				qcom,msm-bus,name = "apps_smmu";

				qcom,msm-bus,num-cases = <2>;

				qcom,msm-bus,active-only;

				qcom,msm-bus,num-paths = <1>;



				qcom,actlr =

					/* For rt TBU +3 deep PF */

					<0x400 0x3ff 0x103>,

					/* For nrt TBU +3 deep PF */

					<0x800 0x3ff 0x103>;



				anoc_1_tbu: anoc_1_tbu@0xc785000 {

					compatible = "qcom,qsmmuv500-tbu";

					reg = <0xc785000 0x1000>,

						<0xc782200 0x8>;

					reg-names = "base", "status-reg";

					qcom,stream-id-range = <0x0 0x400>;

					interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;

					qcom,msm-bus,name = "apps_smmu";

					qcom,msm-bus,num-cases = <2>;

					qcom,msm-bus,active-only;

					qcom,msm-bus,num-paths = <2>;



				};



				mm_rt_tbu: mm_rt_tbu@0xc789000 {

					compatible = "qcom,qsmmuv500-tbu";

					reg = <0xc789000 0x1000>,

						<0xc782208 0x8>;

					reg-names = "base", "status-reg";

					qcom,stream-id-range = <0x400 0x400>;

					interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

					qcom,regulator-names = "vdd";

					qcom,msm-bus,name = "apps_smmu";

					qcom,msm-bus,num-cases = <2>;

					qcom,msm-bus,active-only;

					qcom,msm-bus,num-paths = <2>;



				};



				mm_nrt_tbu: mm_nrt_tbu@0xc78d000 {

					compatible = "qcom,qsmmuv500-tbu";

					reg = <0xc78d000 0x1000>,

						<0xc782210 0x8>;

					reg-names = "base", "status-reg";

					qcom,stream-id-range = <0x800 0x400>;

					interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;

					qcom,regulator-names = "vdd";

					qcom,msm-bus,name = "apps_smmu";

					qcom,msm-bus,num-cases = <2>;

					qcom,msm-bus,active-only;

					qcom,msm-bus,num-paths = <2>;



				};



	};



	kgsl_iommu_test_device {

			compatible = "iommu-debug-test";

			qcom,iommu-dma = "disabled";

			iommus = <&kgsl_smmu 0x7 0x0>;

			status = "disabled";

	};



	apps_iommu_test_device {

			compatible = "iommu-debug-test";

			qcom,iommu-dma = "disabled";

			iommus = <&apps_smmu 0x1E0 0x0>;

			status = "disabled";

	};



	apps_iommu_coherent_test_device {

			compatible = "iommu-debug-test";

			qcom,iommu-dma = "disabled";

			iommus = <&apps_smmu 0x1E1 0x0>;

			dma-coherent;

			status = "disabled";

	};

};

qcom/qrb2210-rb1-idp.dtsi

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#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/iio/qcom,spmi-vadc.h>

#include "qrb2210-rb1-ion.dtsi"



&soc {

	scuba_batterydata: qcom,battery-data {

		qcom,batt-id-range-pct = <15>;

		#include "qg-batterydata-alium-3600mah.dtsi"

		#include "qg-batterydata-atl466271_3300mAh.dtsi"

	};

};



&pm2250_qg {

	qcom,battery-data = <&scuba_batterydata>;

	qcom,qg-iterm-ma = <150>;

	qcom,hold-soc-while-full;

	qcom,linearize-soc;

	qcom,cl-feedback-on;

	qcom,tcss-enable;

	qcom,fvss-enable;

	qcom,fvss-vbatt-mv = <3500>;

	qcom,bass-enable;

};



&pm2250_charger {

	interrupts-extended = <&tlmm 89 0>;

	interrupt-names = "usb_id_irq";

	qcom,usb-id-gpio = <&tlmm 89 0>;



	pinctrl-names = "default";

	pinctrl-0 = <&usb_id_interrupt>;



	qcom,auto-recharge-soc = <98>;

	qcom,suspend-input-on-debug-batt;

	qcom,battery-data = <&scuba_batterydata>;

	io-channels = <&pm2250_vadc ADC5_USB_IN_V_16>,

			<&pm2250_vadc ADC5_CHG_TEMP>;

	io-channel-names = "usb_in_voltage",

			"chg_temp";

	qcom,thermal-mitigation = <2000000 1500000 1000000 500000>;

};

qcom/qrb2210-rb1-ion.dtsi

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#include <dt-bindings/arm/msm/msm_ion_ids.h>

&soc {

	qcom,ion {

		compatible = "qcom,msm-ion";

		#address-cells = <1>;

		#size-cells = <0>;



		system_heap: qcom,ion-heap@25 {

			reg = <ION_SYSTEM_HEAP_ID>;

			qcom,ion-heap-type = "MSM_SYSTEM";

		};



		system_secure_heap: qcom,ion-heap@9 {

			reg = <ION_SECURE_HEAP_ID>;

			qcom,ion-heap-type = "SYSTEM_SECURE";

		};



		qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */

			reg = <ION_SECURE_DISPLAY_HEAP_ID>;

			memory-region = <&secure_display_memory>;

			qcom,ion-heap-type = "HYP_CMA";

		};



		qcom,ion-heap@27 { /* QSEECOM HEAP */

			reg = <ION_QSECOM_HEAP_ID>;

			memory-region = <&qseecom_mem>;

			qcom,ion-heap-type = "DMA";

		};



		qcom,ion-heap@19 { /* QSEECOM HEAP */

			reg = <ION_QSECOM_TA_HEAP_ID>;

			memory-region = <&qseecom_ta_mem>;

			qcom,ion-heap-type = "DMA";

		};

	};

};

qcom/qrb2210-rb1-pinctrl.dtsi

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