Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e835e29d authored by Mike Tipton's avatar Mike Tipton
Browse files

clk: qcom: videocc: Voltage voting support for Lahaina 



Add voltage voting support to the Lahaina VIDEO_CC driver.

Change-Id: If1c943aa067c57b4db813d9e509d5f6b76834505
Signed-off-by: default avatarMike Tipton <mdtipton@codeaurora.org>
parent 1ba0f31f

drivers/clk/qcom/videocc-lahaina.c

+58 −9
Original line number Diff line number Diff line
@@ -24,6 +24,9 @@ 
#include "reset.h"

#include "vdd-level.h"



static DEFINE_VDD_REGULATORS(vdd_mm, VDD_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);



enum {

	P_BI_TCXO,

	P_CHIP_SLEEP_CLK,
@@ -63,6 +66,15 @@ static struct clk_alpha_pll video_pll0 = { 
			.num_parents = 1,

			.ops = &clk_alpha_pll_lucid_5lpe_ops,

		},

		.vdd_data = {

			.vdd_class = &vdd_mx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

		},

	},

};
@@ -93,6 +105,15 @@ static struct clk_alpha_pll video_pll1 = { 
			.num_parents = 1,

			.ops = &clk_alpha_pll_lucid_5lpe_ops,

		},

		.vdd_data = {

			.vdd_class = &vdd_mx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 615000000,

				[VDD_LOW] = 1066000000,

				[VDD_LOW_L1] = 1600000000,

				[VDD_NOMINAL] = 2000000000},

		},

	},

};
@@ -185,6 +206,15 @@ static struct clk_rcg2 video_cc_mvs0_clk_src = { 
		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},

	.clkr.vdd_data = {

		.vdd_class = &vdd_mm,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOWER] = 720000000,

			[VDD_LOW] = 1014000000,

			[VDD_LOW_L1] = 1098000000,

			[VDD_NOMINAL] = 1332000000},

	},

};



static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
@@ -209,6 +239,14 @@ static struct clk_rcg2 video_cc_mvs1_clk_src = { 
		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},

	.clkr.vdd_data = {

		.vdd_class = &vdd_mm,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOWER] = 840000000,

			[VDD_LOW] = 1098000000,

			[VDD_NOMINAL] = 1332000000},

	},

};



static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
@@ -229,6 +267,12 @@ static struct clk_rcg2 video_cc_sleep_clk_src = { 
		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

	},

	.clkr.vdd_data = {

		.vdd_class = &vdd_mm,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_LOWER] = 32000},

	},

};



static struct clk_rcg2 video_cc_xo_clk_src = {
@@ -518,9 +562,22 @@ static int video_cc_lahaina_probe(struct platform_device *pdev) 
{

	struct regmap *regmap;

	struct clk *clk;

	struct regulator *regulator;

	int ret;



	vdd_mm.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mm");

	if (IS_ERR(vdd_mm.regulator[0])) {

		if (PTR_ERR(vdd_mm.regulator[0]) != -EPROBE_DEFER)

			dev_err(&pdev->dev, "Unable to get vdd_mm regulator\n");

		return PTR_ERR(vdd_mm.regulator[0]);

	}



	vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");

	if (IS_ERR(vdd_mx.regulator[0])) {

		if (PTR_ERR(vdd_mx.regulator[0]) != -EPROBE_DEFER)

			dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n");

		return PTR_ERR(vdd_mx.regulator[0]);

	}



	regmap = qcom_cc_map(pdev, &video_cc_lahaina_desc);

	if (IS_ERR(regmap))

		return PTR_ERR(regmap);
@@ -533,14 +590,6 @@ static int video_cc_lahaina_probe(struct platform_device *pdev) 
	}

	devm_clk_put(&pdev->dev, clk);



	regulator = devm_regulator_get(&pdev->dev, "vdd_mm");

	if (IS_ERR(regulator)) {

		if (PTR_ERR(regulator) != -EPROBE_DEFER)

			dev_err(&pdev->dev, "Unable to get vdd_mm regulator\n");

		return PTR_ERR(regulator);

	}

	devm_regulator_put(regulator);



	clk_lucid_5lpe_pll_configure(&video_pll0, regmap, &video_pll0_config);

	clk_lucid_5lpe_pll_configure(&video_pll1, regmap, &video_pll1_config);