Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e813986e authored by Hemant Kumar's avatar Hemant Kumar
Browse files

dt-bindings: arm: msm: Add child node entry for NTN3 i2c client 

In order to access NTN3 switch registers add i2c client properties.
By accessing these registers root complex driver can toggle NTN3
GPIOs to tied to downstream endpoint reset. i2c interface is also
used to dump NTN3 registers for debugging PCIe link related issues.

Change-Id: I38279185c07a2ff7a9736a585f5e84053d459462
parent 8f5224b1

bindings/pci/pci-msm.txt

+50 −0
Original line number Diff line number Diff line
@@ -585,3 +585,53 @@ Example 
			qcom,iommu-cfg = <0x3> /* SMMU PRESENT. SET S1 BYPASS */

			qcom,iommu-range = <0x0 0x10000000 0x0 0x40000000>;

		};



==============

i2c child node

==============



- compatible:

	Usage: required

	Value type: <stringlist>

	Definition: Compatible list, contains

		- "qcom,pcie0-i2c-ntn3" for NTN3 switch attached to Root port 0



- reg:

	Usage: required

	Value type: <u16>

	Definition: i2c slave id



- gpio-config-reg:

	Usage: optional

	Value type: <u32>

	Definition: Slave GPIO configuration register address



- ep-reset-reg:

	Usage: optional

	Value type: <u32>

	Definition: Slave endpoint reset register address



- ep-reset-gpio-mask:

	Usage: optional

	Value type: <u32>

	Definition: Slave GPIO number as 32-bit mask



- dump-regs:

	Usage: optional

	Value Type: Array of <u32>

	Definition: List of slave registers to dump by i2c read



=======

Example

=======



&i2c_3 {

	pcie_i2c_ctrl: pcie_i2c_ctrl {

		compatible = "qcom,pcie0-i2c-ntn3";

		reg = <0x77>;

		gpio-config-reg = <0x801208>;

		ep-reset-reg = <0x801210>;

		ep-reset-gpio-mask = <0xf>;

		dump-regs = <0x801330 0x801350 0x801370>;

	};

};