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Commit e7c6b736 authored by Raghu Ananya Arabolu's avatar Raghu Ananya Arabolu
Browse files

msm: kgsl: Modify CP_LPAC_PROG_FIFO_SIZE register value for A660 



Set the memPoolSize field of CP_LPAC_PROG_FIFO_SIZE register to 32.
memPoolSize is the number of entries in the LPAC Programming Fifo
which replaces the MVC in the CP AC subsystem.

Change-Id: I0d52a07309ce28c231ee3c06f1347a99d3b0391d
Signed-off-by: default avatarRaghu Ananya Arabolu <rarabolu@codeaurora.org>
parent cba97f25

drivers/gpu/msm/adreno_a6xx.c

+1 −1
Original line number Diff line number Diff line
@@ -482,7 +482,7 @@ static void a6xx_start(struct adreno_device *adreno_dev) 
						0x00800060);

		kgsl_regwrite(device, A6XX_CP_LPAC_ROQ_THRESHOLDS_1,

						0x40202016);

		kgsl_regwrite(device, A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000080);

		kgsl_regwrite(device, A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);

	}



	if (adreno_is_a612(adreno_dev) || adreno_is_a610(adreno_dev)) {