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Commit e7932188 authored by Julien Thierry's avatar Julien Thierry Committed by Catalin Marinas
Browse files

arm64: Switch to PMR masking when starting CPUs 



Once the boot CPU has been prepared or a new secondary CPU has been
brought up, use ICC_PMR_EL1 to mask interrupts on that CPU and clear
PSR.I bit.

Since ICC_PMR_EL1 is initialized at CPU bringup, avoid overwriting
it in the GICv3 driver.

Signed-off-by: default avatarJulien Thierry <julien.thierry@arm.com>
Suggested-by: default avatarDaniel Thompson <daniel.thompson@linaro.org>
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent b5cf6073

arch/arm64/kernel/smp.c

+26 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
#include <linux/smp.h>

#include <linux/seq_file.h>

#include <linux/irq.h>

#include <linux/irqchip/arm-gic-v3.h>

#include <linux/percpu.h>

#include <linux/clockchips.h>

#include <linux/completion.h>
@@ -180,6 +181,24 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle) 
	return ret;

}



static void init_gic_priority_masking(void)

{

	u32 cpuflags;



	if (WARN_ON(!gic_enable_sre()))

		return;



	cpuflags = read_sysreg(daif);



	WARN_ON(!(cpuflags & PSR_I_BIT));



	gic_write_pmr(GIC_PRIO_IRQOFF);



	/* We can only unmask PSR.I if we can take aborts */

	if (!(cpuflags & PSR_A_BIT))

		write_sysreg(cpuflags & ~PSR_I_BIT, daif);

}



/*

 * This is the secondary CPU boot entry.  We're using this CPUs

 * idle thread stack, but a set of temporary page tables.
@@ -206,6 +225,9 @@ asmlinkage notrace void secondary_start_kernel(void) 
	 */

	cpu_uninstall_idmap();



	if (system_uses_irq_prio_masking())

		init_gic_priority_masking();



	preempt_disable();

	trace_hardirqs_off();
@@ -426,6 +448,10 @@ void __init smp_prepare_boot_cpu(void) 
	 * and/or scheduling is enabled.

	 */

	apply_boot_alternatives();



	/* Conditionally switch to GIC PMR for interrupt masking */

	if (system_uses_irq_prio_masking())

		init_gic_priority_masking();

}



static u64 __init of_get_cpu_mpidr(struct device_node *dn)

drivers/irqchip/irq-gic-v3.c

+7 −1
Original line number Diff line number Diff line
@@ -415,6 +415,9 @@ static u32 gic_get_pribits(void) 
static bool gic_has_group0(void)

{

	u32 val;

	u32 old_pmr;



	old_pmr = gic_read_pmr();



	/*

	 * Let's find out if Group0 is under control of EL3 or not by
@@ -430,6 +433,8 @@ static bool gic_has_group0(void) 
	gic_write_pmr(BIT(8 - gic_get_pribits()));

	val = gic_read_pmr();



	gic_write_pmr(old_pmr);



	return val != 0;

}
@@ -591,6 +596,7 @@ static void gic_cpu_sys_reg_init(void) 
	group0 = gic_has_group0();



	/* Set priority mask register */

	if (!gic_prio_masking_enabled())

		write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);



	/*