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Commit e761b82e authored by Lucas Stach's avatar Lucas Stach Committed by Shawn Guo
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ARM: dts: imx6: adopt DT to new GPC binding 



Adopt the i.MX6Q/DL DT to the new and more flexible GPC binding.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 1b1ec503

arch/arm/boot/dts/imx6q.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -125,7 +125,7 @@ 
			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,

				 <&clks IMX6QDL_CLK_GPU2D_CORE>;

			clock-names = "bus", "core";

			power-domains = <&gpc 1>;

			power-domains = <&pd_pu>;

		};



		ipu2: ipu@02800000 {

arch/arm/boot/dts/imx6qdl.dtsi

+26 −11
Original line number Diff line number Diff line
@@ -156,7 +156,7 @@ 
				 <&clks IMX6QDL_CLK_GPU3D_CORE>,

				 <&clks IMX6QDL_CLK_GPU3D_SHADER>;

			clock-names = "bus", "core", "shader";

			power-domains = <&gpc 1>;

			power-domains = <&pd_pu>;

		};



		gpu_2d: gpu@00134000 {
@@ -166,7 +166,7 @@ 
			clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,

				 <&clks IMX6QDL_CLK_GPU2D_CORE>;

			clock-names = "bus", "core";

			power-domains = <&gpc 1>;

			power-domains = <&pd_pu>;

		};



		timer@00a00600 {
@@ -434,7 +434,7 @@ 
				clocks = <&clks IMX6QDL_CLK_VPU_AXI>,

					 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;

				clock-names = "per", "ahb";

				power-domains = <&gpc 1>;

				power-domains = <&pd_pu>;

				resets = <&src 1>;

				iram = <&ocram>;

			};
@@ -797,14 +797,29 @@ 
				interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,

					     <0 90 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-parent = <&intc>;

				pu-supply = <&reg_pu>;

				clocks = <&clks IMX6QDL_CLK_IPG>;

				clock-names = "ipg";



				pgc {

					#address-cells = <1>;

					#size-cells = <0>;



					power-domain@0 {

						reg = <0>;

						#power-domain-cells = <0>;

					};

					pd_pu: power-domain@1 {

						reg = <1>;

						#power-domain-cells = <0>;

						power-supply = <&reg_pu>;

						clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,

						         <&clks IMX6QDL_CLK_GPU3D_SHADER>,

						         <&clks IMX6QDL_CLK_GPU2D_CORE>,

						         <&clks IMX6QDL_CLK_GPU2D_AXI>,

						         <&clks IMX6QDL_CLK_OPENVG_AXI>,

						         <&clks IMX6QDL_CLK_VPU_AXI>;

				#power-domain-cells = <1>;

					};

				};

			};



			gpr: iomuxc-gpr@020e0000 {