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Commit e728eabe authored by Jeff Garzik's avatar Jeff Garzik
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[libata] sata_mv: don't touch reserved bits in EDMA config register 



The code in mv_edma_cfg() reflected its 60xx origins, by doing things
[slightly] incorrectly on the older 50xx and newer 6042/7042 chips.

Clean up the EDMA configuration setup such that, each chip family
carefully initializes its own EDMA setup.

Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 616ece2e

drivers/ata/sata_mv.c

+12 −8
Original line number Diff line number Diff line
@@ -814,23 +814,27 @@ static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio) 
	u32 cfg = readl(port_mmio + EDMA_CFG_OFS);



	/* set up non-NCQ EDMA configuration */

	cfg &= ~0x1f;		/* clear queue depth */

	cfg &= ~EDMA_CFG_NCQ;	/* clear NCQ mode */

	cfg &= ~(1 << 9);	/* disable equeue */



	if (IS_GEN_I(hpriv))

	if (IS_GEN_I(hpriv)) {

		cfg &= ~0x1f;		/* clear queue depth */

		cfg |= (1 << 8);	/* enab config burst size mask */

	}



	else if (IS_GEN_II(hpriv))

	else if (IS_GEN_II(hpriv)) {

		cfg &= ~0x1f;		/* clear queue depth */

		cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;

		cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */

	}



	else if (IS_GEN_IIE(hpriv)) {

		cfg |= (1 << 23);	/* dis RX PM port mask */

		cfg &= ~(1 << 16);	/* dis FIS-based switching (for now) */

		cfg |= (1 << 23);	/* do not mask PM field in rx'd FIS */

		cfg |= (1 << 22);	/* enab 4-entry host queue cache */

		cfg &= ~(1 << 19);	/* dis 128-entry queue (for now?) */

		cfg |= (1 << 18);	/* enab early completion */

		cfg |= (1 << 17);	/* enab host q cache */

		cfg |= (1 << 22);	/* enab cutthrough */

		cfg |= (1 << 17);	/* enab cut-through (dis stor&forwrd) */

		cfg &= ~(1 << 16);	/* dis FIS-based switching (for now) */

		cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */

	}



	writelfl(cfg, port_mmio + EDMA_CFG_OFS);